Dimitris Nikolos

发表

Systematic t-error correcting all unidirectional error detecting codes

Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou, 1984, Fehlertolerierende Rechensysteme.

New architectures for modulo 2N - 1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

On the Yield of VLSI Processors with on-chip CPU Cache

Haridimos T. Vergos, Dimitris Nikolos, 1996, EDCC.

Reconfigurable CPU Cache Memory Design : Fault Tolerance and Performance Evaluation

Haridimos T. Vergos, Dimitris Nikolos, Petros Mitsiadis, 1997 .

An efficient comparative concurrent Built-In Self-Test technique

Themistoklis Haniotakis, Constantin Halatsis, Ioannis Voyiatzis, 1995, Proceedings of the Fourth Asian Test Symposium.

A new built-in TPG method for circuits with random patternresistant faults

Spyros Tragoudas, Dimitris Nikolos, Dimitris Bakalis, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Robust test generation for transistor stuck-open faults in CMOS complex gates

Yiorgos Tsiatouhas, Dimitris Nikolos, Antonis Paschalis, 1995 .

Systematic t-Error Correcting/All Unidirectional Error Detecting Codes

Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou, 1984, IEEE Transactions on Computers.

Efficient Modular Design of TSC Checkers for M-out-of-2M Codes

Constantin Halatsis, Antonis M. Paschalis, Dimitris Nikolos, 1988, IEEE Trans. Computers.

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks

Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, 1999, EDCC.

Enhancing dictionary based test data compression using the ATE repeat instruction

Dimitris Nikolos, Panagiotis Sismanoglou, 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).

Conditional soft-edge flip-flop for SET mitigation

Dimitris Nikolos, Panagiotis Sismanoglou, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Sorter Based Permutation Units for Media-Enhanced Microprocessors

Giorgos Dimitrakopoulos, Dimitris Nikolos, Christos Mavrokefalidis, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Spatial pattern prediction based management of faulty data caches

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A class of easily path delay fault testable circuits

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Haridimos T. Vergos, 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

Efficient BIST schemes for RNS datapaths

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

On the design of modulo 2n±1 adders

Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou, 2001, ICECS.

for a Class of Borden Codes

Dimitris Nikolos, Antonis Paschalis, 1995 .

Preemptive built-in self-test for in-field structural testing

Dimitris Nikolos, Panagiotis Sismanoglou, Vlasis Pitsios, 2015, Sixteenth International Symposium on Quality Electronic Design.

A Compact Built-In Current Sensor for IDDQ Testing

Yiorgos Tsiatouhas, Dimitris Nikolos, Th. Haniotakis, 2000 .

Fast and low cost TSC checkers for 1-out-of-n and (n- l)-out-of-n codes in MOS transistor implementation

Dimitris Nikolos, Antonis Paschalis, T. Haniotakis, 1991 .

A new scheme for effective I/sub DDQ/ testing in deep submicron

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2000, Proceedings 2000 IEEE International Workshop on Defect Based Testing (Cat. No.PR00637).

Novel single and double output TSC Berger code checkers

Dimitris Nikolos, Xrysovalantis Kavousianos, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

High speed parallel-prefix modulo 2/sup n/+1 adders for diminished-one operands

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

Extending the viability of I/sub DDQ/ testing in the deep submicron era

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, Proceedings International Symposium on Quality Electronic Design.

Preemptiv eBuilt-I nSelf-Tes tfo rIn-Fiel dStructura lTesting

Dimitris Nikolos, Panagiotis Sismanoglou, Vlasis Pitsios, 2015 .

Deterministic BIST for RNS Adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, IEEE Trans. Computers.

Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Scan cell ordering for low power BIST

Dimitris Nikolos, Dimitris Bakalis, Maciej Bellos, 2004, IEEE Computer Society Annual Symposium on VLSI.

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

New efficient totally self-checking Berger code checkers

Dimitris Nikolos, Xrysovalantis Kavousianos, G. Foukarakis, 1999, Integr..

Synchronization in Scratch: A Case Study with Education Science Students

Dimitris Nikolos, Vassilis Komis, 2015 .

Reseeding-based test set embedding with reduced test sequences

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2005, Sixth international symposium on quality electronic design (isqed'05).

An efficient built-in self test method for robust path delay fault testing

Constantin Halatsis, Ioannis Voyiatzis, Antonis M. Paschalis, 1996, J. Electron. Test..

Proceedings on 3th IEEE International On-Line Testing Workshop (IOLT'97), July 7-9, 1997, Crete, Greece

Michael Nicolaidis, Dimitris Nikolos, A. Paschalis, 1996 .

Efficient Modular Design of TSC Checkers for M-out-of-2M Codes

Constantin Halatsis, Antonis M. Paschalis, Dimitris Nikolos, 1986, Aegean Workshop on Computing.

Self-Testing Embedded Two-Rail Checkers

Dimitris Nikolos, 1998, J. Electron. Test..

Efficient modulo 2/sup n/+1 tree multipliers for diminished-1 operands

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

A versatile built-in self test scheme for delay fault testing

Yiorgos Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Modular TSC checkers for Bose-Lin and Bose codes

Dimitris Nikolos, Xrysovalantis Kavousianos, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

On accumulator-based bit-serial test response compaction schemes

Haridimos T. Vergos, Dimitris Nikolos, Dimitris Bakalis, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Diminished-One Modulo 2n+1 Adder Design

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2002, IEEE Trans. Computers.

Testing combinational iterative logic arrays for realistic faults

Dimitris Gizopoulos, Antonis M. Paschalis, Dimitris Nikolos, 1995, Proceedings 13th IEEE VLSI Test Symposium.

EUDOXUS: a WWW-based generator of reusable arithmetic cores

George Alexiou, Dimitris Nikolos, D. Lymperopoulos, 2001, Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001.

Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient partial scan cell gating for low-power scan-based testing

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2009, TODE.

Fast bit permutation unit for media enhanced microprocessors

Giorgos Dimitrakopoulos, Dimitris Nikolos, Christos Mavrokefalidis, 2006, 2006 IEEE International Symposium on Circuits and Systems.

On-chip deterministic counter-based TPG with low heat dissipation

Spyros Tragoudas, Dimitris Nikolos, Xrysovalantis Kavousianos, 1999, 1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286).

Totally self-checking checkers for Borden codes

Dimitris Gizopoulos, Dimitris Nikolos, Antonis Paschalis, 1994 .

Bit-serial test pattern generation by an accumulator behaving as a non-linear feedback shift register

Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

A Fault Tolerant Dynamic RAM Memory System

Dimitris Nikolos, Antonis Paschalis, Panos Kostarakis, 1987 .

New reseeding technique for LFSR-based test pattern generation

Emmanouil Kalligeros, Dimitris Nikolos, Dimitris Bakalis, 2001, Proceedings Seventh International On-Line Testing Workshop.

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

Emmanouil Kalligeros, Dimitris Nikolos, Dimitris Bakalis, 2002, J. Electron. Test..

On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG

Dimitris Nikolos, Dimitrios Kagaris, P. Karpodinis, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accumulator-based BIST approach for stuck-open and delay fault testing

Constantin Halatsis, Ioannis Voyiatzis, Antonis M. Paschalis, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Area-time efficient modulo 2/sup n/-1 adder design

Costas Efstathiou, Dimitris Nikolos, John Kalamatianos, 1994 .

An Energy-Delay Efficient Subword Permutation Unit

Giorgos Dimitrakopoulos, Dimitris Nikolos, Christos Mavrokefalidis, 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

Multiphase BIST: a new reseeding technique for high test-data compression

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Concurrent detection of soft errors based on current monitoring

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Costas Efstathiou, 2001, Proceedings Seventh International On-Line Testing Workshop.

Testable Designs of Multiple Precharged Domino Circuits

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Costas Efstathiou, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A new test pattern generator for high defect coverage in a BIST environment

Dimitris Nikolos, C. Laoudias, 2004, GLSVLSI '04.

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

Giorgos Dimitrakopoulos, Dimitris Nikolos, Christos Mavrokefalidis, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t

Dimitris Nikolos, Alexandros Krokos, 1992, IEEE Trans. Computers.

An Improved Search Method for Accumulator-Based Test Set Embedding

Dimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros, 2009, IEEE Transactions on Computers.

A hierarchical architecture for concurrent soft error detection based on current sensing

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

Path delay fault testing of ICs with embedded intellectual property blocks

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Haridimos T. Vergos, 1999, DATE '99.

LFSR-based test-data compression with self-stoppable seeds

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

An efficient BIST scheme for high-speed adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Design of High-Speed Low-Power Parallel-Prefix VLSI Adders

Giorgos Dimitrakopoulos, Dimitris Nikolos, P. Kolovos, 2004, PATMOS.

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Emmanouil Kalligeros, Haridimos T. Vergos, George Alexiou, 2002, J. Syst. Archit..

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers

Yiorgos Tsiatouhas, Costas Efstathiou, Dimitris Nikolos, 2003 .

Reprints Available Directly from the Publisher Photocopying Permitted by License Only (c) 2001 Opa (overseas Publishers Association) N.v. Low Power Built-in Self-test Schemes for Array and Booth Multipliers*

Haridimos T. Vergos, George Alexiou, Dimitris Nikolos, 2022 .

Guest Editorial

John P. Hayes, Cecilia Metra, Michael Nicolaidis, 2002, J. Electron. Test..

Test data compression based on the reuse of parts of the dictionary entries

Dimitris Nikolos, Panagiotis Sismanoglou, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An efficient test vector ordering method for low power testing

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2004, IEEE Computer Society Annual Symposium on VLSI.

Design and Analysis of On-Chip CPU Pipelined Caches

Haridimos T. Vergos, Dimitris Nikolos, C. Ninos, 1999, VLSI.

C-testable one-dimensional ILAs with respect to path delay faults: theory and applications

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Dimitris Nikolos, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

Optimal Self-Testing Embedded Parity Checkers

Dimitris Nikolos, 1998, IEEE Trans. Computers.

DV-TSE: Difference Vector Based Test Set Embedding

Dimitris Nikolos, Dimitrios Kagaris, Xrysovalantis Kavousianos, 2003, VLSI-SOC.

On path delay fault testing of multiplexer-based shifters

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Michael Nicolaidis, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches

Haridimos T. Vergos, Dimitris Nikolos, Spyros Voulgaris, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

C-Testable modified-Booth multipliers

Constantin Halatsis, Dimitris Gizopoulos, Antonis M. Paschalis, 1996, J. Electron. Test..

C-testable multipliers based on the modified Booth algorithm

Dimitris Gizopoulos, Dimitris Nikolos, Antonis Paschalis, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

A highly regular multi-phase reseeding technique for scan-based BIST

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2003, GLSVLSI '03.

A ROMless LFSR reseeding scheme for scan-based BIST

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Recovery of performance degradation in defective branch target buffers

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Proceedings on 4th IEEE International On-Line Testing Workshop, July 6-8, Capri, Italy

Michael Nicolaidis, Dimitris Nikolos, M. Sonza Reorda, 1997 .

New design method for low-cost TSC checkers for 1-out-of-n and (n - 1)-out-of-n codes in MOS implementation

Dimitris Nikolos, Antonis Paschalis, Th. Haniotakis, 1990 .

A versatile built-in self test scheme for delay fault testing (poster paper)

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2000, DATE '00.

Low power test set embedding based on phase shifters

Dimitris Nikolos, Dimitrios Kagaris, Maciej Bellos, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Virtual-scan: a novel approach for software-based self-testing of microprocessors

Giorgos Dimitrakopoulos, Dimitris Nikolos, Xrysovalantis Kavousianos, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Test Set Embedding Based on Phase Shifters

Dimitris Nikolos, Dimitrios Kagaris, Maciej Bellos, 2002, EDCC.

A novel fault tolerant cache architecture based on orthogonal latin squares theory

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Accumulator based test-per-scan BIST

Dimitris Nikolos, Dimitrios Kagaris, P. Karpodinis, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Low power dissipation in BIST schemes for modified Booth multipliers

Haridimos T. Vergos, George Alexiou, Dimitris Nikolos, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Optimal Selective Huffman Coding for Test-Data Compression

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2007, IEEE Transactions on Computers.

Deterministic Test Vector Compression / Decompression Using an Embedded Processor

Dimitris Nikolos, Maciej Bellos, 2005, EDCC.

Efficient multiphase test set embedding for scan-based testing

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Fast parallel-prefix modulo 2/sup n/+1 adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2004, IEEE Transactions on Computers.

TRANSFERRING EXPERIENCES IN LOGO-LIKE ENVIRONMENT IN COMPUTATIONAL THINKING GAME DESIGN

Dimitris Nikolos, Vassilis Komis, Anastasia Misirli, 2020 .

Testing CMOS combinational iterative logic arrays for realistic faults

Dimitris Gizopoulos, Antonis M. Paschalis, Dimitris Nikolos, 1996, Integr..

High-speed parallel-prefix VLSI Ling adders

Giorgos Dimitrakopoulos, Dimitris Nikolos, 2005, IEEE Transactions on Computers.

High-Speed Parallel-Prefix Modulo 2n-1 Adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2000, IEEE Trans. Computers.

R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique

Constantin Halatsis, Ioannis Voyiatzis, Antonis M. Paschalis, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Low capture power dictionary-based test data compression

Dimitris Nikolos, Panagiotis Sismanoglou, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Efficient Totally Self-Checking Checkers for a Class of Borden Codes

Themistoklis Haniotakis, Antonis M. Paschalis, Dimitris Nikolos, 1995, IEEE Trans. Computers.

A defect-aware reconfigurable cache architecture for low-Vccmin DVFS-enabled systems

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power aware test-data compression for scan-based testing

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes

Dimitris Nikolos, Xrysovalantis Kavousianos, G. Sidiropoulos, 2000, VLSI Design.

An Accumulator-Based BIST Approach for Two-Pattern Testing

Constantin Halatsis, Ioannis Voyiatzis, Antonis M. Paschalis, 1999, J. Electron. Test..

Efficient diminished-1 modulo 2/sup n/ + 1 multipliers

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2005, IEEE Transactions on Computers.

Path delay fault testing of Benes multistage interconnection networks

Haridimos T. Vergos, Dimitris Nikolos, M. Bellos, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

On TSC Checkers for m-out-n Codes

Vassilios V. Dimakopoulos, Antonis M. Paschalis, Dimitris Nikolos, 1995, IEEE Trans. Computers.

Test data compression based on reuse and bit-flipping of parts of dictionary entries

Dimitris Nikolos, Panagiotis Sismanoglou, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A novel reseeding technique for accumulator-based test pattern generation

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2001, GLSVLSI '01.

A family of parallel-prefix modulo 2/sup n/-1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing

Giorgos Dimitrakopoulos, Dimitris Nikolos, 2005, PATMOS.

A new technique for IDDQ testing in nanometer technologies

Yiorgos Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, 2002, Integr..

Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches

Dimitris Nikolos, Panagiotis Sismanoglou, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An efficient seeds selection method for LFSR-based test-per-clock BIST

Emmanouil Kalligeros, Dimitris Nikolos, Dimitris Bakalis, 2002, Proceedings International Symposium on Quality Electronic Design.

Development of a reusable E1 transceiver suitable for rapid prototyping

George Alexiou, Dimitris Nikolos, Kostas Adaos, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes

Dimitris Nikolos, D. Nikolos, 1991, IEEE Trans. Computers.

On testability of multiple precharged domino logic

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Dimitris Nikolos, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Use Them -Don't Waste Them. Recruiting Strong ECC in L1 Caches for Hard Error Recovery Without the Penalty

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2015, EDCC 2015.

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2015, ACM Great Lakes Symposium on VLSI.

Low power BIST for Wallace tree-based multipliers

Emmanouil Kalligeros, Haridimos T. Vergos, George Alexiou, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Self-exercising self testing k-order comparators

Dimitris Nikolos, Xrysovalantis Kavousianos, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Low power testing by test vector ordering with vector repetition

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

A compact built-in current sensor for I/sub DDQ/ testing

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Dimitris Nikolos, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

On the Yield of VLSI Processors with On-Chip CPU Cache

Haridimos T. Vergos, Dimitris Nikolos, 1999, IEEE Trans. Computers.

Diophantine-equation based arithmetic test set embedding

Dimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Design of compact and high speed totally self-checking CMOS checkers for m-out-of-n codes

Dimitris Nikolos, Xrysovalantis Kavousianos, G. Sidiropoulos, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Run Time Management of Faulty Data Caches

Georgios Keramidas, Dimitris Nikolos, Michail Mavropoulos, 2021, 2021 IEEE European Test Symposium (ETS).

Efficient fault tolerant cache memory design

Haridimos T. Vergos, Dimitris Nikolos, D. Nikolos, 1995, Microprocess. Microprogramming.

Handling zero in diminished-one modulo 2 n + 1 adders

Haridimos T. Vergos, Dimitris Nikolos, Constantinos Efstathiou, 2003 .

Linear-testable and C-testable Nx × Ny modified Booth multipliers

Dimitris Gizopoulos, Dimitris Nikolos, C. Halatsis, 1996 .

Easily testable carry-save multipliers with respect to path delay faults

Michael Nicolaidis, Haridimos T. Vergos, Dimitris Nikolos, 1999 .

Fast C-testable array multipliers

Dimitris Gizopoulos, Dimitris Nikolos, Antonis Paschalis, 1996 .