Chien-Ching Lin

发表

A COFDM baseband processor with robust synchronization for high-speed WLAN applications

Ching-Che Chung, Chen-Yi Lee, Hsuan-Yu Liu, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

MLP/BP-based soft DFEs with bit-interleaved TCM for distorted 16-QAM signal recovery in severe ISI channels

Terng-Yin Hsu, Chien-Ching Lin, Terng-Ren Hsu, 2010, 2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference.

A low-power Reed-Solomon decoder for STM-16 optical communications

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

A 3.33Gb/s (1200,720) low-density parity check code decoder

Hsie-Chia Chang, Chen-Yi Lee, Kai-Li Lin, 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture

Cheng-Chi Wong, Hsie-Chia Chang, Chien-Ching Lin, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications

Chen-Yi Lee, Terng-Yin Hsu, Yuan Chen, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Design and implementation of a reconfigurable architecture for (528, 518) Reed-Solomon codec IP

Hsie-Chia Chang, Wei-Chun Hsu, Chien-Ching Lin, 2005, The 3rd International IEEE-NEWCAS Conference, 2005..

A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network

Shyh-Jye Jou, Hsie-Chia Chang, Chen-Yi Lee, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

A low power and high speed Viterbi decoder chip for WLAN applications

Chen-Yi Lee, Chien-Ching Lin, Chia-Cho Wu, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

An AS-DSP for forward error correction applications

Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

A Universal VLSI Architecture for Reed–Solomon Error-and-Erasure Decoders

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Self-Compensation Technique for Simplified Belief-Propagation Algorithm

Chih-Wei Liu, Hsie-Chia Chang, Yen-Chin Liao, 2007, IEEE Transactions on Signal Processing.

Universal Architectures for Reed-Solomon Error-and-Erasure Decoder

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

A power and area efficient multi-mode FEC processor

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

Cheng-Chi Wong, Hsie-Chia Chang, Chen-Yi Lee, 2010, IEEE Journal of Solid-State Circuits.

Design of a power-reduction Viterbi decoder for WLAN applications

Hsie-Chia Chang, Chen-Yi Lee, Yen-Hsu Shih, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Universal VLSI Architecture for Reed-Solomon

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2009 .

A 480Mb/s LDPC-COFDM-based UWB baseband transceiver

Ching-Che Chung, Hsie-Chia Chang, Chen-Yi Lee, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Multi-mode message passing switch networks applied for QC-LDPC decoder

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A dual mode channel decoder for 3GPP2 mobile wireless communications

Hsie-Chia Chang, Chen-Yi Lee, Yen-Hsu Shih, 2004, Proceedings of the 30th European Solid-State Circuits Conference.

SoC for COFDM Wireless Communications: Challenges and Opportunities

Chen-Yi Lee, Hsuan-Yu Liu, Chien-Ching Lin, 2006, 2006 International Symposium on VLSI Design, Automation and Test.

A low power turbo/Viterbi decoder for 3GPP2 applications

Hsie-Chia Chang, Chen-Yi Lee, Yen-Hsu Shih, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver

Cheng-Chi Wong, Hsie-Chia Chang, Chen-Yi Lee, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Multi-level memory systems using error control codes

Hsie-Chia Chang, Jieh-Tsorng Wu, Chien-Ching Lin, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A high speed Reed–Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

Ching-Che Chung, Hsie-Chia Chang, Chen-Yi Lee, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

A new channel equalizer for OFDM-based wireless communications

Hsie-Chia Chang, Chen-Yi Lee, Chien-Ching Lin, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

A dynamic normalization technique for decoding LDPC codes

Chih-Wei Liu, Hsie-Chia Chang, Yen-Chin Liao, 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications

Chen-Yi Lee, Terng-Yin Hsu, Chien-Ching Lin, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A universal VLSI architecture for bit-parallel computation in GF(2/sup m/)

Hsie-Chia Chang, Chien-Ching Lin, Chen-Yi Lee, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

A long block length bch decoder for DVB-S2 application

Hsie-Chia Chang, Chien-Ching Lin, Yi-Min Lin, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.