Ghassem Jaberipur

发表

Radix-8 full adder in QCA with single clock-zone carry propagation delay

Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur, 2017, Microprocess. Microsystems.

Low area/power decimal addition with carry-select correction and carry-select sum-digits

Ghassem Jaberipur, Morteza Dorrigiv, 2014, Integr..

Fast low energy RNS comparators for 4-moduli sets {2n±1, 2n, m} with m∈{2n+1±1, 2n-1-1}

Ghassem Jaberipur, Zeinab Torabi, G. Jaberipur, 2016, Integr..

Design and evaluation of decimal array multipliers

Behrooz Parhami, Ghassem Jaberipur, Saeid Gorgin, 2009, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers.

A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements

Behrooz Parhami, Dariush Abedi, Ghassem Jaberipur, 2016, 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH).

Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1},2^{n}+2^{n-1}-1,2^{n+1}-1\}$

Ghassem Jaberipur, Bardia Nadimi, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling

Ghassem Jaberipur, Armin Belghadr, G. Jaberipur, 2017, Comput. Electr. Eng..

A Family of High Radix Signed Digit Adders

Ghassem Jaberipur, Saeid Gorgin, 2011, 2011 IEEE 20th Symposium on Computer Arithmetic.

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

Ghassem Jaberipur, Saeid Gorgin, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An improved maximally redundant signed digit adder

Ghassem Jaberipur, Saeid Gorgin, G. Jaberipur, 2010, Comput. Electr. Eng..

Fast division in the residue number system {2n + 1, 2n, 2n-1} based on shortcut mixed radix conversion

Ghassem Jaberipur, Zeinab Torabi, Armin Belghadr, 2020, Comput. Electr. Eng..

Decimal Square Root: Algorithm and Hardware Implementation

Ghassem Jaberipur, Adel Hosseiny, 2016, Circuits Syst. Signal Process..

A ROM-less reverse RNS converter for moduli set {2q±1, 2q±3}

Ghassem Jaberipur, HamidReza Ahmadifar, 2014, IET Comput. Digit. Tech..

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

Behrooz Parhami, Ghassem Jaberipur, 2009, 2009 19th IEEE Symposium on Computer Arithmetic.

FIR Filter Realization via Deferred End-Around Carry Modular Addition

Ghassem Jaberipur, Armin Belghadr, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Decimal Goldschmidt: A hardware algorithm for radix-10 division

Ghassem Jaberipur, Adel Hosseiny, 2016, Comput. Electr. Eng..

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

Behrooz Parhami, Ghassem Jaberipur, 2012, IET Comput. Digit. Tech..

$(4+2\log n)\Delta G$ Parallel Prefix Modulo- $(2^n-3)$ Adder via Double Representation of Residues in [0, 2]

Ghassem Jaberipur, Seyed Hamed Fatemi Langroudi, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

Formal Ambiguity-resolving Syntax Definition with Asserted Shift Reduce Sets

Ghassem Jaberipur, Morteza Dorrigiv, 2013 .

Fully redundant decimal addition and subtraction using stored-unibit encoding

Amir Kaivani, Ghassem Jaberipur, G. Jaberipur, 2010, Integr..

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

Mohammad Ghodsi, Behrooz Parhami, Ghassem Jaberipur, 2006, J. VLSI Signal Process..

Redesigned CMOS (4; 2) compressor for fast binary multipliers

Ali Jahanian, Ghassem Jaberipur, Abdoreza Pishvaie, 2013, Canadian Journal of Electrical and Computer Engineering.

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Behrooz Parhami, Ghassem Jaberipur, Saeid Gorgin, 2010, IEEE Transactions on Computers.

Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies

Behrooz Parhami, Dariush Abedi, Ghassem Jaberipur, 2018, IEEE Transactions on Sustainable Computing.

Modulo-(2^n -- 2^q -- 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues

Ghassem Jaberipur, Seyed Hamed Fatemi Langroudi, G. Jaberipur, 2015, 2015 IEEE 22nd Symposium on Computer Arithmetic.

Improved CMOS (4; 2) compressor designs for parallel multipliers

Ali Jahanian, Ghassem Jaberipur, Abdoreza Pishvaie, 2012, Comput. Electr. Eng..

Improving the speed of decimal division

Amir Kaivani, Ghassem Jaberipur, Adel Hosseiny, 2011, IET Comput. Digit. Tech..

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Ghassem Jaberipur, Saeid Gorgin, Reza Hashemi Asl, 2014, Circuits Syst. Signal Process..

Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding

Ghassem Jaberipur, Morteza Dorrigiv, 2016, Comput. Electr. Eng..

Constant-time addition with hybrid-redundant numbers: Theory and implementations

Behrooz Parhami, Ghassem Jaberipur, B. Parhami, 2008, Integr..

Comment on “High Speed Parallel Decimal Multiplication With Redundant Internal Encodings”

Ghassem Jaberipur, Saeid Gorgin, 2015, IEEE Transactions on Computers.

Extended Redundant-Digit Instruction Set for Energy-Efficient Processors

Ghassem Jaberipur, Saba Amanollahi, G. Jaberipur, 2018, ACM Trans. Embed. Comput. Syst..

Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ

Mohammad Hossein Moaiyeri, Ghassem Jaberipur, M. H. Moaiyeri, 2020, Microelectron. J..

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

Ghassem Jaberipur, Saba Amanollahi, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of diminished-1 encoding on residue number systems arithmetic units and converters

Ghassem Jaberipur, Saeed Nejati, Armin Belghadr, 2019, Comput. Electr. Eng..

Majority-Logic, its applications, and atomic-scale embodiments

Behrooz Parhami, Dariush Abedi, Ghassem Jaberipur, 2020, Comput. Electr. Eng..

On building general modular adders from standard binary arithmetic components

Behrooz Parhami, Ghassem Jaberipur, Saeed Nejati, 2011, 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR).

Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range

Ghassem Jaberipur, Zeinab Torabi, G. Jaberipur, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fully Redundant Decimal Arithmetic

Ghassem Jaberipur, Saeid Gorgin, 2009, 2009 19th IEEE Symposium on Computer Arithmetic.

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture

Amir Kaivani, Ghassem Jaberipur, G. Jaberipur, 2011, Comput. J..

Physically unclonable functions based on small delay defects in QCA

Ghassem Jaberipur, Mohammad Hadi Valavi, G. Jaberipur, 2020, Semiconductor Science and Technology.

Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems

Mohammad Ghodsi, Behrooz Parhami, Ghassem Jaberipur, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic

Behrooz Parhami, Ghassem Jaberipur, B. Parhami, 2007, IET Circuits Devices Syst..

Coplanar QCA serial adder and multiplier via clock-zone based crossover

Dariush Abedi, Ghassem Jaberipur, 2015, 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS).

A Nonspeculative Maximally Redundant Signed Digit Adder

Ghassem Jaberipur, Saeid Gorgin, 2008 .

A New Residue Number System with 5-Moduli Set: {22q, 2q±3, 2q±1}

Ghassem Jaberipur, HamidReza Ahmadifar, 2015, Comput. J..

A fully redundant decimal adder and its application in parallel decimal multipliers

Ghassem Jaberipur, Saeid Gorgin, 2009, Microelectron. J..

Complex exponential functions: A high-precision hardware realization

Ghassem Jaberipur, Adel Hosseiny, 2020, Integr..

Improving the Speed of Parallel Decimal Multiplication

Amir Kaivani, Ghassem Jaberipur, 2009, IEEE Transactions on Computers.

Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues

Ghassem Jaberipur, Sahar Moradi Cherati, 2019, 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH).

Binary-coded decimal digit multipliers

Amir Kaivani, Ghassem Jaberipur, G. Jaberipur, 2007, IET Comput. Digit. Tech..

Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata

Dariush Abedi, Ghassem Jaberipur, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Double {0, 1, 2} representation modulo-(2n − 3) adders

Ghassem Jaberipur, Seyed Hamed Fatemi Langroudi, 2014, IWSSIP 2014 Proceedings.

Fast Energy Efficient Radix-16 Sequential Multiplier

Ghassem Jaberipur, Saba Amanollahi, G. Jaberipur, 2017, IEEE Embedded Systems Letters.

Up to 8k-bit Modular Montgomery Multiplication in Residue Number Systems with Fast 16-bit Residue Channels

Ghassem Jaberipur, Zabihollah Ahmadpour, 2021 .

Balanced minimal latency RNS addition for moduli set {2n −1, 2n, 2n +1}

Ghassem Jaberipur, Saeed Nejati, G. Jaberipur, 2011, 2011 18th International Conference on Systems, Signals and Image Processing.

Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur, 2015, IEEE Transactions on Nanotechnology.

High-performance CMOS (4:2) compressors

Ghassem Jaberipur, Abdoreza Pishvaie, Ali Jahanian, 2014 .

A High Speed Low Power Signed Digit Adder

Ghassem Jaberipur, Saeid Gorgin, G. Jaberipur, 2007 .