Jhih-Yu Jiang

100Gb/s ethernet chipsets in 65nm CMOS technology

Jri Lee, Chen-Lun Lin, Ping-Chuan Chiang, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology

Jri Lee, Chin-Yang Wu, Ping-Chuan Chiang, 2015, IEEE Journal of Solid-State Circuits.

A laser ranging radar transceiver with modulated evaluation clock in 65nm CMOS technology

Jri Lee, Ke-Chung Wu, Jhih-Yu Jiang, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.