Shunsuke Okumura

发表

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, 2012, IEICE Electron. Express.

SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

Yuki Kagiyama, Shunsuke Okumura, Shusuke Yoshimoto, 2011 .

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, Fifteenth International Symposium on Quality Electronic Design.

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2

Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, 2019, 2019 Symposium on VLSI Technology.

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, ISLPED '12.

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM

Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 12th International Symposium on Quality Electronic Design.

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2013, IEICE Trans. Electron..

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Electron..

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 International Reliability Physics Symposium.

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012 .

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Quality of a Bit (QoB): A New Concept in Dependable SRAM

Shunsuke Okumura, Masahiko Yoshimoto, Yasuhiro Morita, 2008, ISQED 2008.

A Dependable SRAM with 7T/14T Memory Cells

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2009, IEICE Trans. Electron..

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Electron..

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2009, 2009 22nd International Conference on VLSI Design.

A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10−19

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2009, 2009 10th International Symposium on Quality Electronic Design.

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2008, IEICE Trans. Electron..

Model-based fault injection for failure effect analysis — Evaluation of dependable SRAM for vehicle control units

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W).

Model-Based Fault Injection for Failure Effect Analysis

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011 .

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

7T SRAM enabling low-energy simultaneous block copy

Shunsuke Okumura, Shusuke Yoshimoto, Yohei Nakata, 2010, IEEE Custom Integrated Circuits Conference 2010.

Quality of a Bit (QoB): A New Concept in Dependable SRAM

Shunsuke Okumura, Masahiko Yoshimoto, Hidehiro Fujiwara, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2.

Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, 2019, 2019 Symposium on VLSI Circuits.

Mo2048 – Unsupervised Machine Learning Based Automatic Demarcation Line Drawing System on Nbi Images of Early Gastric Cancer

Shunsuke Okumura, Satoru Hiwa, Tomoyuki Hiroyasu, 2019 .

Session Initiation Protocol (SIP) Usage of the Offer/Answer Model

Shunsuke Okumura, Paul H. Kyzivat, Takuya Sawada, 2011, RFC.

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores

Shunsuke Okumura, Yohei Nakata, Shintaro Izumi, 2012, ARCS Workshops.

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2012, IEICE Electron. Express.

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, IEICE Trans. Electron..

Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control

Yuki Kagiyama, Shunsuke Okumura, Yohei Nakata, 2011, 2011 12th International Symposium on Quality Electronic Design.