Yohei Nakata

发表

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Failure Modes and Effects Analysis Using Virtual Prototyping System with Microcontroller Model for Automotive Control System

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013 .

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, 2012, IEICE Electron. Express.

SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

Yuki Kagiyama, Shunsuke Okumura, Shusuke Yoshimoto, 2011 .

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, Fifteenth International Symposium on Quality Electronic Design.

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2013, IEICE Trans. Electron..

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Overview of AIWolfDial 2019 Shared Task: Contest of Automatic Dialog Agents to Play the Werewolf Game through Conversations

Yohei Nakata, Hirotaka Osawa, Takashi Otsuki, 2019 .

Model-based fault injection for failure effect analysis — Evaluation of dependable SRAM for vehicle control units

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W).

Model-Based Fault Injection for Failure Effect Analysis

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2011 .

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015 .

7T SRAM enabling low-energy simultaneous block copy

Shunsuke Okumura, Shusuke Yoshimoto, Yohei Nakata, 2010, IEEE Custom Integrated Circuits Conference 2010.

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

Shunsuke Okumura, Yohei Nakata, Masahiko Yoshimoto, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Design of SRAM Resilient Against Dynamic Voltage Variations

Yohei Nakata, Koji Nii, Masahiko Yoshimoto, 2019 .

Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2013, International Symposium on Quality Electronic Design (ISQED).

Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores

Shunsuke Okumura, Yohei Nakata, Shintaro Izumi, 2012, ARCS Workshops.

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Electron..

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, IEICE Trans. Electron..

Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive Electronic Control Systems

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2019 .

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, ARCS Workshops.

Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control

Yuki Kagiyama, Shunsuke Okumura, Yohei Nakata, 2011, 2011 12th International Symposium on Quality Electronic Design.