J. E. N. Abhilash

Implementation Of Fully-Pipelined 16-Point DHT Architectures Using 8-Point And 4-Point DHTs for FPGA Realization

J. Sridevi, J. E. N. Abhilash, J. Vasanta Kumar, 2012 .

FPGA Realization of Secured Hash Algorithm with Parallel Architecture

M. Rambabu, J. E. N. Abhilash, N. Srikanth, 2013 .

FPGA Implementation of Blowfish Cryptosystem Using VHDL

P. Suresh Kumar, J. E. N. Abhilash, L. Kranthi Kiran, 2013 .

A Novel Approach of Modified Run Length Encoding Scheme for High Speed Data Communication Application

J. E. N. Abhilash, N. Srikanth, S. Joseph, 2013 .