Hamid R. Zarandi

发表

Hierarchical Binary Set Partitioning in Cache Memories

Hamid Sarbazi-Azad, Hamid R. Zarandi, 2005, The Journal of Supercomputing.

An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems

Hamid R. Zarandi, Hananeh Aliee, H. Aliee, 2011, EWDC '11.

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

Dhiraj K. Pradhan, Costas Argyrides, Hamid R. Zarandi, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Two Efficient Software Techniques to Detect and Correct Control-Flow Errors

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies

Hamid R. Zarandi, Mohammad Maghsoudloo, H. Zarandi, 2014, Microprocess. Microsystems.

A High Performance, Multi-Bit Output Logic-in-Memory Adder

Nader Bagherzadeh, Hamid R. Zarandi, Javad Talafy, 2021, IEEE Transactions on Emerging Topics in Computing.

A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip

Hamid R. Zarandi, Fatemeh Khalili, H. Zarandi, 2013, 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations

Hossein Pedram, Alireza Tajary, Behnam Ghavami, 2010, PATMOS.

Control-flow error recovery using commodity multi-core architecture features

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

An Adaptive Redundancy Oriented Method to Tolerate Soft Errors in SRAM-Based FPGAs Using Unused Resources

Hamid R. Zarandi, Somayeh Bahramnejad, 2010, 2010 International Conference on Availability, Reliability and Security.

A Cluster-Based Method to Detect and Correct Anomalies in Sensor Data of Embedded Systems

Hamid R. Zarandi, Roghayeh Mojarad, Hossain Kordestani, 2016, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP).

Design space exploration of non-uniform cache access for soft-error vulnerability mitigation

Hamid R. Zarandi, Mohammad Maghsoudloo, H. Zarandi, 2015, Microelectron. Reliab..

Using instruction result locality and re-execution to mitigate silent data corruptions

Alireza Tajary, Hamid R. Zarandi, 2016, Microelectron. Reliab..

IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA

Jimson Mathew, Seyed Ghassem Miremadi, Hamid R. Zarandi, 2007 .

A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs

Morteza Saheb Zamani, Hamid R. Zarandi, Hassan Ebrahimi, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

HYSTERY: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems

Hamid R. Zarandi, Athena Abdi, H. Zarandi, 2018, The Journal of Supercomputing.

A parallel clustering algorithm on the star graph and its performance

Hamid Sarbazi-Azad, Hamid R. Zarandi, Mahdi Fazeli, 2013, Math. Comput. Model..

Reducing of soft error effects on a MIPS-based dual-core processor

Hamid R. Zarandi, Moslem Didehban, Saman Khoshbakht, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

A fault-tolerant cache architecture based on binary set partitioning

Seyed Ghassem Miremadi, Hamid R. Zarandi, 2006, Microelectron. Reliab..

ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores

Alain Girault, Hamid R. Zarandi, athena abdi, 2019, IEEE Transactions on Parallel and Distributed Systems.

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

Dhiraj K. Pradhan, Jimson Mathew, Seyed Ghassem Miremadi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays

Hamid R. Zarandi, Hossein Bardareh, Amir M. Hajisadeghi, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

A cross-layer aging-aware task scheduling approach for multiprocessor embedded systems

Hamid R. Zarandi, Athena Abdi, Masoomeh Karami, 2018, Microelectron. Reliab..

Fault injection-based evaluation of a synchronous NoC router

Hossein Pedram, Pooria M. Yaghini, Hamid R. Zarandi, 2009, 2009 15th IEEE International On-Line Testing Symposium.

Fxy: a Hierarchical Routing Algorithm to Balance Performance and Fault Tolerance in Networks-on-Chip

Hamid R. Zarandi, Saleh Fakhrali, H. Zarandi, 2014, J. Circuits Syst. Comput..

Mitigation of soft errors in SRAM-based FPGAs using CAD tools

Hamid R. Zarandi, Somayeh Bahramnejad, 2011, Comput. Electr. Eng..

A Quad Router design for next-generation CMPs

Hamid R. Zarandi, Hannaneh Aliee, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs

Dhiraj K. Pradhan, Seyed Ghassem Miremadi, Costas Argyrides, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays

Hamid R. Zarandi, Hananeh Aliee, H. Aliee, 2013, IEEE Transactions on Reliability.

A Highly Fault Detectable Cache Architecture for Dependable Computing

Seyed Ghassem Miremadi, Hamid R. Zarandi, 2004, SAFECOMP.

Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire

Hamid R. Zarandi, Ronak Salamat, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs

Hamid R. Zarandi, Lei Jiang, Farzaneh Zokaee, 2018, IEEE Computer Architecture Letters.

Analysis of the soft error effects on CAN network controller

Hamid R. Zarandi, Saman Khoshbakht, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

A fault-tolerant core mapping technique in networks-on-chip

Hamid R. Zarandi, Fatemeh Khalili, 2013, IET Comput. Digit. Tech..

ERPOT: A quad-criteria scheduling heuristic to optimize the execution time, failure rate, power consumption and temperature in multicores

Alain Girault, Hamid R. Zarandi, Athena Abdi, 2019 .

A SEU-protected cache memory-based on variable associativity of sets

Seyed Ghassem Miremadi, Hamid R. Zarandi, 2007, Reliab. Eng. Syst. Saf..

Lifetime Reliability Enhancement in Multiprocessor Systems Through a Fine-Grained System-Level Approach

Hamid R. Zarandi, Athena Abdi, Masoomeh Karami, 2019, J. Circuits Syst. Comput..

Process variation-aware performance analysis of asynchronous circuits

Hossein Pedram, Behnam Ghavami, Mohsen Raji, 2010, Microelectron. J..

Low-Cost Software-Implemented Error Detection Technique

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2011, 2011 International Symposium on Electronic System Design.

Power-aware branch target prediction using a new BTB architecture

Hamid R. Zarandi, Hamid Sarbazi-Azad, Hadi Sadeghi, 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

A Fault Injection Attitude based on Background Debug Mode in Embedded Systems

Hossein Pedram, Seyyed Amir Asghari, Mohammad Khademi, 2009, CDES.

Hierarchical multiple associative mapping in cache memories

Seyed Ghassem Miremadi, Hamid R. Zarandi, S. Miremadi, 2005, 12th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems (ECBS'05).

Series memristors: A hardened memory cell design against read faults

Hamid R. Zarandi, Mohammad Rasekh Jahromi, Peiman Pourmomen, 2015, 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS).

Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution

Hamid R. Zarandi, Javad Talafy, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Investigation of Transient Fault Effects in an Asynchronous NoC Router

Hossein Pedram, Pooria M. Yaghini, Hamid R. Zarandi, 2010, 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing.

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

Hossein Pedram, Alireza Tajary, Behnam Ghavami, 2011, Des. Autom. Embed. Syst..

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories

Hamid R. Zarandi, Javad Talafy, Amir M. Hajisadeghi, 2020, Microprocess. Microsystems.

Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets

Hamid R. Zarandi, Ronak Salamat, Hamed Abbasitabar, 2012, 2012 IEEE 15th International Conference on Computational Science and Engineering.

Context-Aware Anomaly Detection in Embedded Systems

Hamid R. Zarandi, Fatemeh Ehsani-Besheli, 2017, DepCoS-RELCOMEX.

Fault injection into verilog models for dependability evaluation of digital systems

Seyed Ghassem Miremadi, Alireza Ejlali, Hamid R. Zarandi, 2003, Second International Symposium on Parallel and Distributed Computing, 2003. Proceedings..

Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs

Hamid R. Zarandi, Elham Cheshmikhani, 2016, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP).

MWPF: A Deadlock Avoidance Fully Adaptive Routing Algorithm in Networks-on-Chip

Hamid R. Zarandi, Kamran Nasiri, 2016, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP).

Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation

Hossein Pedram, Behnam Ghavami, Mohsen Raji, 2009, PATMOS.

An analysis of fault effects and propagations in ZPU: The world's smallest 32 bit CPU

Hamid R. Zarandi, Mahroo Zandrahimi, Alireza Rohani, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk

Farnad Nasirzadeh, Shahab Shoar, Hamid R. Zarandi, 2017, Qual. Reliab. Eng. Int..

Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols

Hamid R. Zarandi, Mohammad Maghsoudloo, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Hierarchical Set-Associate Cache for High-Performance and Low-Energy Architecture

Seyed Ghassem Miremadi, Hamid R. Zarandi, 2006, J. Circuits Syst. Comput..

IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes

Alireza Tajary, Nader Bagherzadeh, Hamid R. Zarandi, 2020, Microprocess. Microsystems.

CCDA: Correcting control-flow and data errors automatically

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Control-flow error detection using combining basic and program-level checking in commodity multi-core architectures

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2011, 2011 6th IEEE International Symposium on Industrial and Embedded Systems.

Two effective anomaly correction methods in embedded systems

Hamid R. Zarandi, Roghayeh Mojarad, H. Zarandi, 2015, 2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST).

A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models

Seyed Ghassem Miremadi, Shaahin Hessabi, Alireza Ejlali, 2004, ESA/VLSI.

Fault tree analysis using stochastic logic: A reliable and high speed computing

Hananeh Aliee, Hamid R. Zarandi, H. Aliee, 2011, 2011 Proceedings - Annual Reliability and Maintainability Symposium.

DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors

Hamid R. Zarandi, Mohammad H. Mottaghi, H. Zarandi, 2014, Microprocess. Microsystems.

Quantitative assessment of risks on construction projects using fault tree analysis with hybrid uncertainties

Farnad Nasirzadeh, Shahab Shoar, Hamid R. Zarandi, 2019, Construction Innovation.

Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodes in Digital Circuits

Hamid R. Zarandi, Maryam Ghane, 2016, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP).

MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits

Hamid R. Zarandi, Hossein Bardareh, Amir M. Hajisadeghi, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Postponing wearout failures in chip multiprocessors using thermal management and thread migration

Ann Gordon-Ross, Hamid R. Zarandi, Elham Kashefi, 2016, 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

Soft error propagations and effects analysis on CAN controller

Hamid R. Zarandi, Saman Khoshbakht, 2010, 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR).

A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-based Multiprocessors

Hamid R. Zarandi, Fatemeh Khalili, 2012, 2012 IEEE 15th International Conference on Computational Science and Engineering.

Cache vulnerability mitigation using an adaptive cache coherence protocol

Hamid R. Zarandi, Mohammad Maghsoudloo, 2014, The Journal of Supercomputing.

Fault detection enhancement in cache memories using a high performance placement algorithm

Hamid Sarbazi-Azad, Seyed Ghassem Miremadi, Hamid R. Zarandi, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Analysis of Transient Faults on a MIPS-Based Dual-Core Processor

Hamid R. Zarandi, Moslem Didehban, Iman Faraji, 2010, 2010 International Conference on Availability, Reliability and Security.

DUSTER: DUal Source Write TERmination Method for STT-RAM Memories

Hamid R. Zarandi, Javad Talafy, Amir M. Hajisadeghi, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

A Probabilistic Method to Detect Anomalies in Embedded Systems

Alireza Zarei, Hamid R. Zarandi, Mahroo Zandrahimi, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes

Morteza Saheb Zamani, Hamid R. Zarandi, Hassan Ebrahimi, 2011, Microelectron. J..

Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme

Seyed Ghassem Miremadi, Hamid R. Zarandi, 2005, LADC.

Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays

Hamid R. Zarandi, Farzaneh Zokaee, Hossein Bardareh, 2017, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Fault injection into SRAM-based FPGAs for the analysis of SEU effects

Seyed Ghassem Miremadi, Alireza Ejlali, Hossein Asadi, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs

Seyed Ghassem Miremadi, Hamid R. Zarandi, 2007, Microelectron. Reliab..

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

Hamid R. Zarandi, Alireza Rohani, 2010, Microelectron. Reliab..

An Efficient Soft Error Detection in Multicore Processors Running Server Applications

Alireza Tajary, Hamid R. Zarandi, H. Zarandi, 2016, 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP).

Fault tolerance assessment of PIC microcontroller based on fault injection

Pooria M. Yaghini, Hamid R. Zarandi, Ashkan Eghbal, 2009, 2009 10th Latin American Test Workshop.

An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L)

Hamid R. Zarandi, Alireza Rohani, 2009, 2009 International Conference on Availability, Reliability and Security.

Dependability analysis using a fault injection tool based on synthesizability of HDL models

Seyed Ghassem Miremadi, Alireza Ejlali, Hamid R. Zarandi, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs

Dhiraj K. Pradhan, Jimson Mathew, Seyed Ghassem Miremadi, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors

Hamid R. Zarandi, Hananeh Aliee, H. Aliee, 2011, SAFECOMP.

Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

Hamid R. Zarandi, Elham Cheshmikhani, 2015, Microelectron. Reliab..

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs

Dhiraj K. Pradhan, Seyed Ghassem Miremadi, Costas Argyrides, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Accelerating accurate fault tree analysis using HW/SW co-design

Hamid R. Zarandi, Hananeh Aliee, Elham Cheshmikhani, 2014, 2014 Reliability and Maintainability Symposium.

A hybrid fault injection approach based on simulation and emulation co-operation

Seyed Ghassem Miremadi, Alireza Ejlali, Siavash Bayat Sarmadi, 2003, 2003 International Conference on Dependable Systems and Networks, 2003. Proceedings..

A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs

Hamid R. Zarandi, Alireza Rohani, 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs

Seyed Ghassem Miremadi, Alireza Ejlali, Hossein Asadi, 2004, 10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings..

Markov-Based Anomaly Correction in Embedded Systems

Hamid R. Zarandi, Roghayeh Mojarad, H. Zarandi, 2016 .

New Switch Box Architecture for SEU Detection in SRAM-Based FPGAs

Hamid R. Zarandi, Mahroo Zandrahimi, Alireza Rohani, 2009, 2009 2nd International Conference on Computer Science and its Applications.

Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2011, 2011 14th Euromicro Conference on Digital System Design.

Multiple Upsets Tolerance in SRAM Memory

Dhiraj K. Pradhan, Costas Argyrides, Hamid R. Zarandi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

Hossein Pedram, Pooria M. Yaghini, Hamid R. Zarandi, 2011, J. Syst. Archit..

An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2012, Microelectron. Reliab..

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs

Dhiraj K. Pradhan, Jimson Mathew, Seyed Ghassem Miremadi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Two effective methods to detect anomalies in embedded systems

Hamid R. Zarandi, Mahroo Zandrahimi, Mohammad H. Mottaghi, 2012, Microelectron. J..

An Investigation of Fault Tolerance Behavior of 32-Bit DLX Processor

Pooria M. Yaghini, Hamid R. Zarandi, Saeedeh Eskandari, 2009, 2009 Second International Conference on Dependability.

CPU-aware, process-level redundancy to tolerate faults in multi-core

Alireza Tajary, Hamid R. Zarandi, Hananeh Aliee, 2011, 2011 International Conference on High Performance Computing & Simulation.

Mitigating and tolerating SEU effects in switch modules of SRAM-based FPGAs

Hamid R. Zarandi, Alireza Rohani, 2009, 2009 5th Southern Conference on Programmable Logic (SPL).

A fault-aware low-energy spare core allocation in networks-on-chip

Hamid R. Zarandi, Fatemeh Khalili, 2012, NORCHIP 2012.

Leveraging the Potential of Control-Flow Error Resilient Techniques in Multithreaded Programs pdf

Hamid R. Zarandi, Mohammad Maghsoudloo, Navid Khoshavi, 2016, ArXiv.

Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip

Hamid R. Zarandi, Saleh Fakhrali, 2016, J. Circuits Syst. Comput..

CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics

Hamid R. Zarandi, Amir M. Hajisadeghi, 2021 .