Jean-Pierre David

发表

Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique

Yvon Savaria, Ahmed Chiheb Ammari, Aref Trigui, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Effective FPGA-based electric motor modeling with floating-point cores

Christian Dufour, Jean Belanger, Jean-Pierre David, 2010, IECON 2010 - 36th Annual Conference on IEEE Industrial Electronics Society.

Design patterns for recording and analysing usage of learning systems: State of art of tracking and analysing usage.

Vanda Luengo, Jean-Michel Adam, Christophe Choquet, 2005 .

POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA

Ahmed M. Abdelsalam, J. M. Pierre Langlois, Ahmed Elsheikh, 2018, 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP).

Setting up On-Line Learning Experiments: The LearningLab Platform

Sandra Michelet, Jean-Michel Adam, Christian Martel, 2008, 2008 Eighth IEEE International Conference on Advanced Learning Technologies.

Programmable architectures for subband coding : FPGA-based systems versus dedicated VLSI chip

Jean-Didier Legat, Pierre Desneux, Jean-Pierre David, 1998 .

Hypermedia Exercises Prototyping and Modelising

Jean-Pierre David, André Cogne, Annick Dutel, 1996, CALISCE.

A FPGA-Based Implementation of Adaptive Sound Filtering

Jean-Didier Legat, Jean-Pierre David, 1998 .

Architecture synchronisée par les données pour systèmes reconfigurables

Jean-Didier Legat, Jean-Pierre David, J. David, 2001 .

Guidelines for the support of the experiments through the SVL. Task Instrumentation and development of uses and best experimental practices

Vanda Luengo, Jean-Michel Adam, Jacqueline Bourdeau, 2005 .

A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA

Jean-Pierre David, Mathieu Allard, Patrick Grogan, 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

Training deep neural networks with low precision multiplications

Yoshua Bengio, Jean-Pierre David, Matthieu Courbariaux, 2014 .

A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management

Yvon Savaria, Meng Li, Guchuan Zhu, 2018, IEEE Access.

POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests

Ahmed M. Abdelsalam, J. M. Pierre Langlois, Jean-Pierre David, 2019, 2019 Conference on Design and Architectures for Signal and Image Processing (DASIP).

Low latency and division free Gauss-Jordan solver in floating point arithmetic

Jean-Pierre David, 2017, J. Parallel Distributed Comput..

A step towards intelligent translation from high-level design to RTL

Etienne Bergeron, Jean-Pierre David, 2004 .

Max-hashing fragments for large data sets detection

Jean-Pierre David, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

A data-flow oriented co-design for reconfigurable systems

Jean-Didier Legat, Jean-Pierre David, 1998, Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237).

Fast description and synthesis of control-dominant circuits

Jean-Pierre David, Marc-André Daigneault, 2014, Comput. Electr. Eng..

Raising the abstraction level of HDL for control-dominant applications

Jean-Pierre David, Marc-André Daigneault, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Modeling Collaborative Learning Activities on e-Learning Platforms

Christine Ferraris, Christian Martel, Jean-Pierre David, 2006, Sixth IEEE International Conference on Advanced Learning Technologies (ICALT'06).

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA

Jean-Pierre David, Marc-André Daigneault, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

A step towards intelligent translation from high-level design to RTL

Etienne Bergeron, Jean-Pierre David, 2004, 4th IEEE International Workshop on System-on-Chip for Real-Time Applications.

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Jean-Pierre David, Tarek Ould Bachir, J. David, 2013, TRETS.

An Intermediate Level HDL for System Level Design

Etienne Bergeron, Jean-Pierre David, 2004, FDL.

Low latency solver for linear equation systems in floating point arithmetic

Jean-Pierre David, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Low precision arithmetic for deep learning pdf

Yoshua Bengio, Jean-Pierre David, Matthieu Courbariaux, 2014, ICLR.

DISSERTATION ON THE EFFECTS OF MOTION AND REST IN SURGICAL DISEASES

Jean-Pierre David, 1916 .

FPGA-based real-time simulation of state-space models using floating-point cores

Jean-Pierre David, Tarek Ould Bachir, J. David, 2010, Proceedings of 14th International Power Electronics and Motion Control Conference EPE-PEMC 2010.

Ultra-low latency communication channels for FPGA-based HPC cluster

Jean-Pierre David, Roberto Sanchez Correa, J. David, 2018, Integr..

Bit-Slicing FPGA Accelerator for Quantized Neural Networks

Yvon Savaria, Jean-Pierre David, Olexa Bilaniuk, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Expressing Workshop Scenario with Computer Independent Model

Jean-Pierre David, Anne Lejeune, Emmanuelle Villiot-Leclercq, 2006, Sixth IEEE International Conference on Advanced Learning Technologies (ICALT'06).

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

Jean-Pierre David, Tarek Ould-Bachir, Federico Montano, 2020, Electronics.

A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2002, FPL.

RISC-V Barrel Processor for Accelerator Control

Yvon Savaria, Jean-Pierre David, Olexa Bilaniuk, 2020, 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)

Jean-Pierre David, Marc-André Daigneault, 2013, FPGA '13.

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs

Marc Feeley, Etienne Bergeron, Jean-Pierre David, 2008, CC.

Trails of Digital and Non-Digital LOs

Mark Levene, Lydia Montandon, Judith Schoonenboom, 2004 .

Expressing Learning Scenarios with Computer Independent Models

Jean-Pierre David, Anne Lejeune, Emmanuelle Villiot-Leclercq, 2006, Sixth IEEE International Conference on Advanced Learning Technologies (ICALT'06).

Design of a Multi-FPGA System for Rapid Prototyping Experimentation

Jean-Didier Legat, Jean-Pierre David, 1998 .

Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation

Marc Feeley, Etienne Bergeron, Jean-Pierre David, 2011, TRETS.

An FPGA Implementation of the Linear Cryptanalysis

Jean-Didier Legat, Jean-Jacques Quisquater, François-Xavier Standaert, 2002, FPL.

Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision

Jean-Pierre David, Tarek Ould Bachir, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

Comparing Educational Modeling Languages on a Case Study

Christine Ferraris, Christian Martel, Jean-Pierre David, 2006, Sixth IEEE International Conference on Advanced Learning Technologies (ICALT'06).

Two-level configuration for FPGA: A new design methodology based on a computing fabric

Yvon Savaria, Jean-Pierre David, Mathieu Allard, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors

J. M. Pierre Langlois, Jean-Pierre David, Sivakumar Chidambaram, 2018, 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP).

A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits

Jean Mahseredjian, Jean-Pierre David, Tarek Ould Bachir, 2013, Math. Comput. Simul..

A Multi-FPGA System for Prototyping Power Conscious Algorithms

Jean-Didier Legat, Jean-Pierre David, Ricardo Ferreira, 2000 .

A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications

Yvon Savaria, Guchuan Zhu, Jean-Pierre David, 2017, 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC).

BinaryConnect: Training Deep Neural Networks with binary weights during propagations

Yoshua Bengio, Jean-Pierre David, Matthieu Courbariaux, 2015, NIPS.

Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver

Jean-Pierre David, Marc-André Daigneault, 2015, 2015 IEEE International Parallel and Distributed Processing Symposium Workshop.

Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)

Jean-Pierre David, Marc-André Daigneault, J. David, 2010, FPGA '10.

POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees

Ahmed M. Abdelsalam, J. M. Pierre Langlois, Ahmed Elsheikh, 2020, J. Signal Process. Syst..

Mapping applications on two-level configurable hardware

Yvon Savaria, Himan Khanzadi, Jean-Pierre David, 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration

Jean-Pierre David, Marc-André Daigneault, 2011, IEEE Transactions on Instrumentation and Measurement.

Synchronized-transfer-level design methodology applied to hardware matrix multiplication

Jean-Pierre David, Marc-André Daigneault, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

Application Specific Instruction set processor specialized for block motion estimation

J. M. Pierre Langlois, Jean-Pierre David, Marc-André Daigneault, 2008, 2008 IEEE International Conference on Computer Design.

Hardware Complexity of Modular Multiplication and Exponentiation

Kassem Kalach, Jean-Pierre David, Nicolas Tittley, 2007, IEEE Transactions on Computers.

LDL: An Alternative EML

Christine Ferraris, Christian Martel, Jean-Pierre David, 2006, Sixth IEEE International Conference on Advanced Learning Technologies (ICALT'06).

Automated Synthesis of Streaming Transfer Level Hardware Designs

Jean-Pierre David, Marc-André Daigneault, J. David, 2018, ACM Trans. Reconfigurable Technol. Syst..

Effective floating-point calculation engines intended for the FPGA-based HIL simulation

Jean Mahseredjian, Jean-Pierre David, Tarek Ould Bachir, 2012, 2012 IEEE International Symposium on Industrial Electronics.

A data driven CGRA Overlay Architecture with embedded processors

Yvon Savaria, Himan Khanzadi, Jean-Pierre David, 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).

A multi-FPGA based coprocessor for digital signal processing

Jean-Didier Legat, Jean-Pierre David, 1998 .

RISC-V Barrel Processor for Deep Neural Network Acceleration

Yvon Savaria, Jean-Pierre David, Olexa Bilaniuk, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020

Manuel J. Barragan Asian, Jean-Pierre David, 2021, IEEE Trans. Circuits Syst. I Regul. Pap..

Floating-Point Engines for the FPGA-Based Real-Time Simulation of Power Electronic Circuits

Jean Mahseredjian, Christian Dufour, Jean-Pierre David, 2011 .