A. Devgan

Characterizing the impact of different memory-intensity levels

R. Kotla, A. Devgan, S. Ghiasi, 2004, IEEE International Workshop on Workload Characterization, 2004. WWC-7. 2004.

Sleep transistor sizing using timing criticality and temporal currents

Bin Zhang, D.Z. Pan, A. Devgan, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Interconnect design and analysis issues in high performance ICs

A. Devgan, 2001, ICCAD 2001.

Simulation of coupling capacitances using matrix partitioning

A. Devgan, T.V. Nguyen, A. Sadigh, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Leakage and leakage sensitivity computation for combinational circuits

Y. Liu, A. Devgan, S. Nassif, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

Block-based static timing analysis with uncertainty

A. Devgan, C. Kashyap, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell

Ching-Te Chuang, A. Devgan, S. Mukhopadhyay, 2004, Proceedings of the 30th European Solid-State Circuits Conference.

Efficient techniques for gate leakage estimation

A. Devgan, R.M. Rao, J.L. Burns, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..