J. Cai

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

N. Loubet, P. Kulkarni, H. Bu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Stacked devices for SEU immune design

P. Oldiges, L. Wissel, D. Heidel, 2010, 2010 IEEE International SOI Conference (SOI).

Semiconductor-On-Insulator lateral bipolar transistors for high-speed low-power applications

J. Cai, Jeng-Bang Yau, T. H. Ning, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).