S. Ponoth

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

N. Loubet, P. Kulkarni, H. Bu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Extremely thin SOI (ETSOI) technology: Past, present, and future

P. Kulkarni, H. Bu, A. Khakifirooz, 2010, 2010 IEEE International SOI Conference (SOI).

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Physical, Electrical, and Reliability Characterization of Ru for Cu Interconnects

C.-K. Hu, C.-C. Yang, L. Gignac, 2006, 2006 International Interconnect Technology Conference.

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

N. Loubet, A. Khakifirooz, Kangguo Cheng, 2012, IEEE Electron Device Letters.

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

R. Augur, G. Biery, S. Arai, 2006, 2006 International Electron Devices Meeting.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Role of CU in TDDB of Low-K Dielectrics

S. Ponoth, S. Cohen, E. Liniger, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

BEOL Integration of Highly Damage -Resistant Porous Ultra Low-K Material Using Direct CMP and Via-first Process

J. Gill, T. Spooner, S. Ponoth, 2006, 2006 International Interconnect Technology Conference.