B. Doris

发表

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Extremely thin SOI (ETSOI) technology: Past, present, and future

P. Kulkarni, H. Bu, A. Khakifirooz, 2010, 2010 IEEE International SOI Conference (SOI).

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

O. Rozeau, O. Faynot, G. Ghibaudo, 2014, 2014 IEEE International Electron Devices Meeting.

Device design considerations for next generation CMOS technology: Planar FDSOI and FinFET (Invited)

M. Vinet, A. Khakifirooz, K. Cheng, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Extreme scaling with ultra-thin Si channel MOSFETs

H.-S.P. Wong, Ying Zhang, Leathen Shi, 2002, Digest. International Electron Devices Meeting,.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

P. Oldiges, B. Haran, H. Bu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

N. Loubet, A. Khakifirooz, Kangguo Cheng, 2012, IEEE Electron Device Letters.

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

S. Narasimha, N. Zamdmer, J. Bruley, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Woo-Hyeong Lee, S.K.H. Fung, P. Agnello, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

D. Mocuta, Y. Toyoshima, B.H. Lee, 2003, IEEE International Electron Devices Meeting 2003.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs

H.-S.P. Wong, P. Oldiges, T. Kanarsky, 2002, IEEE Electron Device Letters.

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

M. Raymond, M. Burkhardt, S. Paparao, 2008, 2008 IEEE International Electron Devices Meeting.

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

N. Loubet, T. Yamashita, J. A. Ott, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).