Natesan Venkateswaran

发表

Clock-skew constrained placement for row based designs

Dinesh Bhatia, Natesan Venkateswaran, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Timing analysis with nonseparable statistical and deterministic variations

Jinjun Xiong, Vladimir Zolotov, Jeffrey G. Hemmett, 2012, DAC Design Automation Conference 2012.

Optimization objectives and models of variation for statistical gate sizing

Dennis Sylvester, Vladimir Zolotov, Richard B. Brown, 2005, ACM Great Lakes Symposium on VLSI.

A distributed timing analysis framework for large designs

Martin D. F. Wong, Tsung-Wei Huang, Natesan Venkateswaran, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Gate sizing using incremental parameterized statistical timing analysis

Vladimir Zolotov, Natesan Venkateswaran, Matthew R. Guthaus, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Congestion mitigation during placement

Kanad Chakraborty, Natesan Venkateswaran, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

First-Order Incremental Block-Based Statistical Timing Analysis

Natesan Venkateswaran, Kaushik Ravindran, Kerim Kalafala, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Criticality computation in parameterized statistical timing

Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Reversible statistical max/min operation: Concept and applications to timing

Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, 2012, DAC Design Automation Conference 2012.

A constructive method for data path area estimation during high-level VLSI synthesis

Dinesh Bhatia, Ranga Vemuri, Anurag Gupta, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Star sensor/Earth sensor updated gyro reference for precision pointing spacecraft

M. Seetharama Bhat, Natesan Venkateswaran, E. Krishna Kumar, 1993 .

Clock-skew constrained cell placement

Dinesh Bhatia, Natesan Venkateswaran, 1996, Proceedings of 9th International Conference on VLSI Design.

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains

Vladimir Zolotov, Natesan Venkateswaran, Debjit Sinha, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

A Survey of SSTA Techniques with Focus on Accuracy and Speed

Sachin S. Sapatnekar, Vladimir Zolotov, Daniel K. Beece, 2017 .