Andrea Pallotta

发表

A monolithic GaAs clock and data recovery circuit for 2.5 Gb/s NRZ data stream

Francesco Centurelli, Alessandro Trifiletti, Andrea Pallotta, 1997 .

Silicon-based phased locked loop (PLL) clock recovery to regenerate 2.5-Gbit/s NRZ data

Andrea Pallotta, 1995, Other Conferences.

Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications

Francesco Centurelli, Alessandro Trifiletti, Luigi Boccia, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

1.29-W/mm2 23-dBm 66-GHz Power Amplifier in 55-nm SiGe BiCMOS With In-Line Coplanar Transformer Power Splitters and Combiner

Domenico Zito, Domenico Pepe, Luca Larcher, 2017, IEEE Microwave and Wireless Components Letters.