Bob Verbruggen

发表

Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"

Jan Craninckx, Takaya Yamamoto, Piet Wambacq, 2015, IEEE J. Solid State Circuits.

A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Journal of Solid-State Circuits.

Session 28 overview: Hybrid ADCs

Tai-Cheng Lee, Un-Ku Moon, Bob Verbruggen, 2017, ISSCC.

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

Dimitri Linten, Jonathan Borremans, Steven Thijs, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A programmable RFSoC in 16nm FinFET technology for wideband communications

Bob Verbruggen, Liam Madden, Patrick Lynch, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

Jonathan Borremans, Jan Craninckx, Björn Debaillie, 2011, IEEE Journal of Solid-State Circuits.

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC

Jan Craninckx, Piet Wambacq, Badr Malki, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS

Jan Craninckx, Badr Malki, Bob Verbruggen, 2013, 2013 Symposium on VLSI Circuits.

High-speed analog-to-digital converters in downscaled CMOS

Stefano D'Amico, Annachiara Spagnolo, Piet Wambacq, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET

Alonso Morgado, Bob Verbruggen, Patrick Lynch, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

Jan Craninckx, Geert Van der Plas, Piet Wambacq, 2009, IEEE Journal of Solid-State Circuits.

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

Stefano D'Amico, Annachiara Spagnolo, Piet Wambacq, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

Low-Cost CMOS-Based Receive Modules for 60 GHz Wireless Communication

Jonathan Borremans, Andre Bourdoux, Piet Wambacq, 2009, 2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium.

Digitally Assisted Analog to Digital Converters

Bob Verbruggen, 2015 .

A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS

Jan Craninckx, Bob Verbruggen, Masao Iriguchi, 2012, 2012 IEEE International Solid-State Circuits Conference.

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

Bob Verbruggen, John McGrath, Bruno Vaz, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

High-Speed ADCs for Wireless Base Stations

Alonso Morgado, Bob Verbruggen, Brian Long, 2020 .

A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

Jonathan Borremans, Jan Craninckx, Ewout Martens, 2014, IEEE Journal of Solid-State Circuits.

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

Jan Craninckx, Geert Van der Plas, Piet Wambacq, 2010, IEEE Journal of Solid-State Circuits.

A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range

Jan Craninckx, Takaya Yamamoto, Piet Wambacq, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs

Ying Cao, Yohan Frans, Parag Upadhyaya, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)

Bernhard Wicht, Payam Heydari, Youngcheol Chae, 2019, IEEE J. Solid State Circuits.

A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS

Jan Craninckx, Badr Malki, Bob Verbruggen, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass \Sigma \Delta ADC in 90nm CMOS

Liesbet Van der Perre, Jonathan Borremans, Jan Craninckx, 2008 .

A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC

Bob Verbruggen, Ryan Kinnerk, Bruno Vaz, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

Jan Craninckx, Bob Verbruggen, Masao Iriguchi, 2012, IEEE Journal of Solid-State Circuits.

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS

Jan Craninckx, Geert Van der Plas, Piet Wambacq, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication

Chunshu Li, André Bourdoux, Piet Wambacq, 2016, IEEE Journal of Solid-State Circuits.

A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC

Geert Van der Plas, Bob Verbruggen, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz

Anthony Collins, Bob Verbruggen, Patrick Lynch, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

Jan Craninckx, Takaya Yamamoto, Ewout Martens, 2015, IEEE Journal of Solid-State Circuits.

The Potential of FinFETs for Analog and RF Circuit Applications

Dimitri Linten, Nadine Collaert, Jonathan Borremans, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

Jan Craninckx, Takaya Yamamoto, Piet Wambacq, 2014, IEEE Journal of Solid-State Circuits.

A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS

Geert Van der Plas, Bob Verbruggen, 2008, IEEE Journal of Solid-State Circuits.

A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS

Stefano D'Amico, Annachiara Spagnolo, Piet Wambacq, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 2.4 GHz Low-Power Sixth-Order RF Bandpass $\Delta\Sigma$ Converter in CMOS

Jonathan Borremans, Jan Craninckx, Geert Van der Plas, 2009, IEEE Journal of Solid-State Circuits.

A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS

Jan Craninckx, Geert Van der Plas, Piet Wambacq, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers

Jonathan Borremans, Jan Craninckx, Mark Ingels, 2011, 2011 IEEE International Solid-State Circuits Conference.

Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee

Chih-Cheng Hsieh, John Keane, Bob Verbruggen, 2021, ISSCC.

7 A 7 . 4to-14 GHz PLL with 54 fsrms Jitter in 16 nm FinFET for Integrated RF-Data-Converter SoCs

Yohan Frans, Parag Upadhyaya, Ken Chang, 2018 .

6 A 40 nm CMOS Highly Linear 0 . 4to-6 GHz Receiver Resilient to 0 dBm Out-of-Band Blockers

Jonathan Borremans, Jan Craninckx, Mark Ingels, 2011 .