M. Edahiro

Delay Minimization For Zero-skew Routing

M. Edahiro, M. Edahiro, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Triple-CPU Mobile Application Processor Chip

Naoki Nishi, Junji Sakai, Tatsuya Tokue, 2005 .

Minimum skew and minimum path length routing in VLSI layout design

M. Edahiro, M. Edahiro, 1991 .

New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

Y. Hayashi, M. Edahiro, S. Kobayashi, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).