Thomas M. Niermann

Compaction of ATPG-generated test sequences for sequential circuits

Janak H. Patel, Jacob A. Abraham, Resve A. Saleh, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

PROOFS: a fast, memory-efficient sequential circuit fault simulator

Janak H. Patel, Wu-Tung Cheng, Thomas M. Niermann, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A genetic algorithm framework for test generation

Elizabeth M. Rudnick, Janak H. Patel, Thomas M. Niermann, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Methods for reducing events in sequential circuit fault simulation

Elizabeth M. Rudnick, Janak H. Patel, Thomas M. Niermann, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Test compaction for sequential circuits

Janak H. Patel, Jacob A. Abraham, Rabindra K. Roy, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

HITEC: a test generation package for sequential circuits

Janak H. Patel, Thomas M. Niermann, J. Patel, 1991, Proceedings of the European Conference on Design Automation..

Proofs: a fast, memory efficient sequential circuit fault simulator

Janak H. Patel, Wu-Tung Cheng, Thomas M. Niermann, 1991, DAC '90.

Sequential Circuit Test Generation in a Genetic Algorithm Framework

Elizabeth M. Rudnick, Janak H. Patel, Thomas M. Niermann, 1994, 31st Design Automation Conference.