D.D. Caviglia

An on-chip learning neural network

G.M. Bo, D.D. Caviglia, M. Valle, 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium.

Efficient emulation of neural networks on concurrent architectures for optimization problems

D.D. Caviglia, E. Di Zitti, G.M. Bisio, 1990, IEEE International Symposium on Circuits and Systems.

A VLSI architecture for weight perturbation on chip learning implementation

G.M. Bo, D.D. Caviglia, M. Valle, 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium.

An Experimental Analog Chip for Real-time Image Processing

D.D. Caviglia, M. Valle, F. Oddone, 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

A Symbolic Cell Synthesizer for CMOS IC Design

D.D. Caviglia, F. Curatelli, R. Costa, 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.

Analysis of neural algorithms for parallel architectures

D.D. Caviglia, E. Di Zitti, G.M. Bisio, 1989, IEEE International Symposium on Circuits and Systems,.