C. Liu

发表

Design and Verification of an FPGA-based Bit Error Rate Tester

Futian Liang, Annie Xiang, D Gong, 2012 .

Development of A 16:1 serializer for data transmission at 5 Gbps

D Gong, Suen Hou, C. Liu, 2009 .

The Design of a High Speed Low Power Phase Locked Loop

Suen Hou, C. Liu, Tiankuan Liu, 2009 .

The Latency Validation of the Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade

Wei Zhou, C. Liu, Jingbo Ye, 2018 .

LOCx2-130, a low-power, low-latency, 2 × 4.8-Gbps serializer ASIC for detector front-end readout

C. Liu, Jingbo Ye, A. C. Xiang, 2018, Journal of Instrumentation.

Link model simulation and power penalty specification of the versatile link systems

D Gong, C. Liu, A. Prosser, 2011 .

High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers

D Gong, Suen Hou, C. Liu, 2009 .

Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade

Xiaoting Li, D Gong, Suen Hou, 2017 .

Developments of Two High-speed Dual-channel VCSEL Driver ASICs

Wei Zhou, Guangming Huang, D Gong, 2018 .

LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

Guangming Huang, C. Liu, Tiankuan Liu, 2016 .