Maciej J. Ciesielski

发表

Arithmetic Bit-Level Verification Using Network Flow Model

André Rossi, Maciej J. Ciesielski, Walter Brown, 2013, Haifa Verification Conference.

Efficient parallel verification of Galois field multipliers

Cunxi Yu, Maciej J. Ciesielski, M. Ciesielski, 2016, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

BDS: a BDD-based logic optimization system

Maciej J. Ciesielski, Congguang Yang, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A fast two-pass HDL simulation with on-demand dump

Jaebum Kim, Seiyang Yang, Kyuho Shim, 2008, 2008 Asia and South Pacific Design Automation Conference.

Algorithms for Taylor expansion diagrams [IC design/verification applications]

Rolf Drechsler, Görschwin Fey, Maciej J. Ciesielski, 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

PLA decomposition with generalized decoders

Seiyang Yang, Maciej J. Ciesielski, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Transistor level placement for full custom datapath cell design

Maciej J. Ciesielski, Durgam Vahia, 1999, ISPD '99.

Two-Dimensional Routing for the Silc Silicon Compiler

Maciej J. Ciesielski, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Elimination of multi-cycle false paths by state encoding

Maciej J. Ciesielski, Zafar Hasan, Z. Hasan, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Reverse engineering of irreducible polynomials in GF(2m) arithmetic

Daniel E. Holcomb, Cunxi Yu, Maciej J. Ciesielski, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

PLADE: a two-stage PLA decomposition

Seiyang Yang, Maciej J. Ciesielski, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automatic word-level abstraction of datapath

Cunxi Yu, Maciej J. Ciesielski, M. Ciesielski, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A unified approach to input-output encoding for FSM state assignment

Maciej J. Ciesielski, Marc Davio, Jia-Jye Shen, 1991, 28th ACM/IEEE Design Automation Conference.

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams

Emmanuel Boutillon, Maciej J. Ciesielski, Dusung Kim, 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

Priyank Kalla, Maciej J. Ciesielski, Serkan Askar, 2006, IEEE Transactions on Computers.

Formal Verification of Arithmetic Circuits by Function Extraction

André Rossi, Duo Liu, Cunxi Yu, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analyzing Imprecise Adders Using BDDs -- A Case Study

Cunxi Yu, Maciej J. Ciesielski, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams

Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Clock period minimization with wave pipelining

Maciej J. Ciesielski, Donald A. Joy, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Placement for clock period minimization with multiple wave propagation

Maciej J. Ciesielski, Donald A. Joy, 1991, 28th ACM/IEEE Design Automation Conference.

Mathematical framework for representing discrete functions as word-level polynomials

Dhiraj K. Pradhan, Maciej J. Ciesielski, Serkan Askar, 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

Fast STA prediction-based gate-level timing simulation

Maciej J. Ciesielski, Tariq B. Ahmad, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A now state assignment technique for testing and low power

Sungju Park, Sangwook Cho, Seiyang Yang, 2004, Proceedings. 41st Design Automation Conference, 2004..

Retiming-based factorization for sequential logic optimization

Maciej J. Ciesielski, Surendra Bommu, Niall O'Neill, 2000, TODE.

High-Level Dataflow Transformations Using Taylor Expansion Diagrams

Emmanuel Boutillon, Maciej J. Ciesielski, Daniel Gomez-Prado, 2009, IEEE Design & Test of Computers.

Digraph Relaxation for 2-Dimensional Placement of IC Blocks

Maciej J. Ciesielski, Edwin Kinnen, M. Ciesielski, 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Spectral approach to verifying non-linear arithmetic circuits

Cunxi Yu, Maciej J. Ciesielski, Atif Yasin, 2019, ASP-DAC.

Optimization of Data-Flow Computations Using Canonical TED Representation

Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Advanced datapath synthesis using graph isomorphism

Cunxi Yu, Maciej J. Ciesielski, Andrew Sullivan, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Verification of gate-level arithmetic circuits by function extraction

André Rossi, Duo Liu, Cunxi Yu, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Strategies for solving the Boolean satisfiability problem using binary decision diagrams

Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski, 2001, J. Syst. Archit..

Wave-pipelining: a tutorial and research survey

W. Liu, Wayne P. Burleson, Fabian Klass, 1998, IEEE Trans. Very Large Scale Integr. Syst..

FPGA latency optimization using system-level transformations and DFG restructuring

Maciej J. Ciesielski, Russell Tessier, Daniel Gomez-Prado, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A fast partitioning method for PLA-based FPGAs

David Harrison, Maciej J. Ciesielski, Zafar Hasan, 1992, IEEE Design & Test of Computers.

Fast time-parallel C-based event-driven RTL simulation

Maciej J. Ciesielski, Tariq B. Ahmad, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Finite state machine decomposition using multiway partitioning

Maciej J. Ciesielski, Maya K. Yajnik, M. Ciesielski, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Fast computation of data correlation using BDDs

Zhihong Zeng, Ian G. Harris, Qiushuang Zhang, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

LPSAT: a unified approach to RTL satisfiability

Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Variable ordering for taylor expansion diagrams

Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

Maciej J. Ciesielski, Tariq B. Ahmad, T. B. Ahmad, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Analytical approach to custom datapath design

Maciej J. Ciesielski, Serkan Askar, M. Ciesielski, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

A comprehensive approach to the partial scan problem using implicitstate enumeration

Priyank Kalla, Maciej J. Ciesielski, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads

Maciej J. Ciesielski, Tariq B. Ahmad, T. B. Ahmad, 2013, 2013 14th International Workshop on Microprocessor Test and Verification.

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers

Cunxi Yu, Maciej J. Ciesielski, Atif Yasin, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

DAG-aware logic synthesis of datapaths

Cunxi Yu, Maciej J. Ciesielski, Andrew Sullivan, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Design validation of behavioral VHDL descriptions for arbitrary fault models

Ian G. Harris, Fei Xin, Maciej J. Ciesielski, 2005, European Test Symposium (ETS'05).

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits

Xiangyu Zhang, Daniel E. Holcomb, Duo Liu, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Functional Retiming: A New Approach to Sequential Synthesis and Optimization

Maciej J. Ciesielski, 1996 .

Testability of sequential circuits with multi-cycle false paths

Priyank Kalla, Maciej J. Ciesielski, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, J. Low Power Electron..

Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering pdf

Cunxi Yu, Maciej J. Ciesielski, 2018, ArXiv.

MULTES: Multilevel Temporal-Parallel Event-Driven Simulation

Seiyang Yang, Maciej J. Ciesielski, Dusung Kim, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Metamorphosis: state assignment by retiming and re-encoding

Maciej J. Ciesielski, Balakrishnan Iyer, 1996, Proceedings of International Conference on Computer Aided Design.

Layer assignment for VLSI interconnect delay minimization

Maciej J. Ciesielski, M. Ciesielski, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Data-Flow Transformations using Taylor Expansion Diagrams

Emmanuel Boutillon, Maciej J. Ciesielski, Daniel Gomez-Prado, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

High-level design verification using Taylor Expansion Diagrams: first results

Priyank Kalla, Emmanuel Boutillon, Eric Martin, 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

Function Extraction from Arithmetic Bit-Level Circuits

André Rossi, Duo Liu, Maciej J. Ciesielski, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 24th Internatioal Conference on VLSI Design.

Functional Test Generation using Constraint Logic Programming

Zhihong Zeng, Bruno Rouzeyre, Maciej J. Ciesielski, 2001, VLSI-SOC.

A BDD-based satisfiability infrastructure using the unate recursive paradigm

Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski, 2000, DATE '00.

A new distributed event-driven gate-level HDL simulation by accurate prediction

Seiyang Yang, Maciej J. Ciesielski, Dusung Kim, 2011, 2011 Design, Automation & Test in Europe.

Formal Verification Using Don't-Care and Vanishing Polynomials

Cunxi Yu, Maciej J. Ciesielski, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Taylor expansion diagrams: a new representation for RTL verification

Zhihong Zeng, Priyank Kalla, Bruno Rouzeyre, 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

Analytical approach to layout generation of datapath cells

Maciej J. Ciesielski, Serkan Askar, Samuel Levitin, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Temporal parallel simulation: A fast gate-level HDL simulation using higher level models

Seiyang Yang, Kyuho Shim, Maciej J. Ciesielski, 2011, 2011 Design, Automation & Test in Europe.

BDD decomposition for efficient logic synthesis

Maciej J. Ciesielski, Vigyan Singhal, Congguang Yang, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

An Optimum Layer Assignment for Routing in ICs and PCBs

Maciej J. Ciesielski, Edwin Kinnen, 1981, 18th Design Automation Conference.

Functional verification and simulation of FSM networks

Maciej J. Ciesielski, Zafar Hasan, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Yield-aware floorplanning

Israel Koren, Maciej J. Ciesielski, Zhaojun Wo, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Optimizing data flow graphs to minimize hardware implementation

Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification

Zhihong Zeng, Priyank Kalla, Bruno Rouzeyre, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

A comprehensive approach to the partial scan problem using implicit state enumeration

Priyank Kalla, Maciej J. Ciesielski, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

The best constant approximant operators in Lorentz spaces Gammap, w and their applications

Maciej J. Ciesielski, Anna Kaminska, A. Kamińska, 2010, J. Approx. Theory.

Functional test generation based on word-level SAT

Zhihong Zeng, Maciej J. Ciesielski, Kesava R. Talupuru, 2005, J. Syst. Archit..

Exploiting Circuit Duality to Speed up SAT

Giovanni De Micheli, Alan Mishchenko, Luca Gaetano Amarù, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Simulation Acceleration with HW Re-Compilation Avoidance

Seiyang Yang, Kyuho Shim, Maciej J. Ciesielski, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Intelligent Simulation for Computer Aided Design of Optical Networks

Andrea Fumagalli, Imrich Chlamtac, Chester A. Ruszczyk, 1997, ONDM.

Wave-pipelining: is it practical?

Wayne P. Burleson, Fabian Klass, Maciej J. Ciesielski, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

An ILP formulation for yield-driven architectural synthesis

Israel Koren, Maciej J. Ciesielski, Zhaojun Wo, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Logic Debugging of Arithmetic Circuits

Duo Liu, Cunxi Yu, Maciej J. Ciesielski, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Reencoding for cycle-time minimization under fixed encoding length

Maciej J. Ciesielski, Balakrishnan Iyer, 1998, ICCAD.

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Gi-Joon Nam, Cunxi Yu, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Verification of arithmetic datapath designs using word-level approach — A case study

Cunxi Yu, Maciej J. Ciesielski, Walter Brown, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Synthesis for mixed CMOS/PTL logic (poster paper)

Maciej J. Ciesielski, Congguang Yang, 2000, DATE '00.

Algebraic approach to arithmetic design verification

André Rossi, Maciej J. Ciesielski, Tariq B. Ahmad, 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

An Analytical Method for Compacting Routing Area in Integrated Circuits

Maciej J. Ciesielski, Edwin Kinnen, 1982, 19th Design Automation Conference.

Rewriting Environment for Arithmetic Circuit Verification

Alan Mishchenko, Cunxi Yu, Maciej J. Ciesielski, 2018, LPAR.

Temporal parallel gate-level timing simulation

Seiyang Yang, Kyuho Shim, Maciej J. Ciesielski, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization

Seiyang Yang, Maciej J. Ciesielski, M. Ciesielski, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis

Cunxi Yu, Maciej J. Ciesielski, Atif Yasin, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Performance driven resynthesis by exploiting retiming-induced state register equivalence

Priyank Kalla, Maciej J. Ciesielski, M. Ciesielski, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

BDS: a BDD-based logic optimization system

Maciej J. Ciesielski, Vigyan Singhal, Congguang Yang, 2000, DAC.