Walter Brown

Arithmetic Bit-Level Verification Using Network Flow Model

André Rossi, Maciej J. Ciesielski, Walter Brown, 2013, Haifa Verification Conference.

Formal Verification of Arithmetic Circuits by Function Extraction

André Rossi, Duo Liu, Cunxi Yu, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Innovations for digital inclusion: Leveraging next generation networks for human development from the bottom of the pyramid

Walter Brown, Walter Brown, 2009, 2009 ITU-T Kaleidoscope: Innovations for Digital Inclusions.

Towards a research framework for a human development-based "bottom of the pyramid" ICT development strategy in South Africa

Irwin Brown, Walter Brown, I. Brown, 2009, ECIS.

Verification of gate-level arithmetic circuits by function extraction

André Rossi, Duo Liu, Cunxi Yu, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

The Benefits of Using a Computer Workstation for Information ntensive Classes

Walter Brown, Edward L. Vockell, 1996 .

Function Extraction from Arithmetic Bit-Level Circuits

André Rossi, Duo Liu, Maciej J. Ciesielski, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Next generation ICT policy in South Africa: Towards a human development-based ICT policy

Irwin Brown, Walter Brown, 2008, HCC.

Logic Debugging of Arithmetic Circuits

Duo Liu, Cunxi Yu, Maciej J. Ciesielski, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Verification of arithmetic datapath designs using word-level approach — A case study

Cunxi Yu, Maciej J. Ciesielski, Walter Brown, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).