P. Restle

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Yu Cao, Xuejue Huang, Tsu-Jae King, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

Design and implementation of the POWER5/spl trade/ microprocessor

N. Schwartz, S. Runyon, D. Plass, 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

When are transmission-line effects important for on-chip interconnections

K.A. Jenkins, G.V. Kopcsay, C.W. Surovic, 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.

CMOS high speed ECL receivers

S. Schuster, R. Franch, P. Restle, 1987, 1987 Symposium on VLSI Circuits.

Challenges and solutions in the design of high-frequency global clock distributions [Tutorial 5]

P. Restle, K. Shepard, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Dealing with inductance in high-speed chip design

A. Ruehli, P. Restle, S.G. Walker, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).