Kai Esmark

Kai Esmark, Reinhold Gaertner, Friedrich Zur Nieden, 2017, 2017 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMCCompo).

Integrated circuits with ESD-resistant capacitor and manufacturing processes

Harald Gossner, Christian Russ, Kai Esmark, 2005 .

Advanced 2D/3D ESD device simulation-a powerful tool already used in a pre-Si phase

Wolfgang Fichtner, Wolfgang Stadler, Kai Esmark, 2001, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Junjun Li, Ralph Halbach, Christian Russ, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

ESD circuit simulation

Harald Gossner, Wolfgang Stadler, Kai Esmark, 2003 .

Analysis of forward recovery in GGNMOS devices under fast transients

Stefan Decker, Kai Esmark, Filippo Magrini, 2018, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

Michael Graf, Wolfgang Wilkening, Wolfgang Stadler, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies

A. Sieck, Wolfgang Stadler, Kai Esmark, 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

High abstraction level permutational ESD concept analysis

Doris Schmitt-Landsiedel, Wolfgang Stadler, Kai Esmark, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Operating method for semiconductor component

Harald Gossner, Wolfgang Stadler, Kai Esmark, 2002 .

Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection structures

Dionyz Pogany, Erich Gornik, G. Groos, 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

Chapter 1 – ESD basics

Kai Esmark, 2003 .

Chip-level ESD verification

Harald Gossner, Wolfgang Stadler, Kai Esmark, 2003 .

Device simulation of ESD protection elements

Kai Esmark, 2001 .

CDM tests on interface test chips for the verification of ESD protection concepts

Wolfgang Stadler, Kai Esmark, T. Brodbeck, 2007 .

Chapter 8 - Outlook

Harald Gossner, Wolfgang Stadler, Kai Esmark, 2003 .

ESD induced functional upset in magnetic sensor ICs

Mario Motz, Kai Esmark, Stefan Jahn, 2015, 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

SCR operation mode of diode strings for ESD protection

Wolfgang Fichtner, Christian Russ, Kai Esmark, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Chapter 3 – Simulation flow

Kai Esmark, 2003 .

Using CC-TLP to get a CDM robustness value

Kai Esmark, Heinrich Wolf, Horst Gieser, 2015, 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Triggering of transient latch-up (TLU) by system level ESD

Wolfgang Stadler, Kai Esmark, Tilo Brodbeck, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

ESD compact-simulation: investigation of inverter failure

Harald Gossner, Wolfgang Stadler, Doris Schmitt-Landsiedel, 2003 .

Laser-Interferometric Investigation of Triggering Behavior in CMOS and Smart Power ESD Protection Structures

Sergey Bychikhin, Dionyz Pogany, Erich Gornik, 2001 .

ESD device simulation

Harald Gossner, Wolfgang Stadler, Kai Esmark, 2003 .

Reliability aspects of gate oxide under ESD pulse stress

Thomas Pompl, Wolfgang Stadler, Kai Esmark, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Predict the product specific CDM stress using measurement-based models of CDM discharge heads

Kai Esmark, Friedrich zur Nieden, Reinhold Gartner, 2016, 2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry

Sergey Bychikhin, Dionyz Pogany, Erich Gornik, 2002 .

Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

Dionyz Pogany, Erich Gornik, Harald Gossner, 2000 .

Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique

Dionyz Pogany, Erich Gornik, G. Groos, 2000 .

Characterization and investigation of the interaction between hot electron and electrostatic discharge stresses using NMOS devices in 0.13 /spl mu/m CMOS technology

Akram A. Salman, Dimitris E. Ioannou, Kai Esmark, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry

Dionyz Pogany, Erich Gornik, Wolfgang Fichtner, 2000 .