Khyati Nanda

I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA

Kartik Kalia, Khyati Nanda, Arushi Aggarwal, 2015 .

Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

Kartik Kalia, Khyati Nanda, Arushi Aggarwal, 2015 .

HSTL based low power thermal aware adder design on 65nm FPGA

Bishwajeet Pandey, Kartik Kalia, Khyati Nanda, 2015, 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom).

GTL based wireless sensor specific energy efficient ALU design on 65nm FPGA

Bishwajeet Pandey, Kartik Kalia, Khyati Nanda, 2015, 2015 International Conference on Signal Processing, Computing and Control (ISPCC).

HSTL IO Standard Based Energy Efficient FIR Filter Design on 28nm FPGA

Jasleen Kaur, Khyati Nanda, Shivani Madhok, 2015 .