S. Iijima

A 1.28 μm2 bit-line shielded memory cell technology for 64 Mb DRAMs

Y. Nakagome, T. Kure, T. Kisu, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)

T. Nishida, T. Kure, K. Shimohigashi, 1992, IEEE Electron Device Letters.

A 64 GHz Si bipolar transistor using in-situ phosphorus doped polysilicon emitter technology

Tokuo Kure, M. Tanabe, S. Iijima, 1991, International Electron Devices Meeting 1991 [Technical Digest].