Jaume Segura

发表

Analysis and future trends of Iddq testing for silicon on insulator CMOS ICs

Denis Flandre, Jean-Pierre Raskin, Benjamin Iniguez, 2001 .

A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates

Jaume Segura, José Luis Rosselló, 2003, PATMOS.

Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment

A. Comerma, Jaume Segura, Lluís Garrido, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

Jaume Segura, Gabriel Torrens, Sebastià A. Bota, 2014, Microelectron. Reliab..

Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources

J. M. Quesada, M. C. Jiménez-Ramos, Jaume Segura, 2017, Microelectron. Reliab..

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs

Jaume Segura, Josep L. Rosselló, C. de Benito, 2007 .

Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era

Peter C. Maxwell, Jaume Segura, 2002, IEEE Des. Test Comput..

View from the bottom: nanometer technology AC parametric failures - why, where, and how to detect

Ali Keshavarzi, Jaume Segura, Charles F. Hawkins, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell

Víctor H. Champac, Jaume Segura, Sebastià A. Bota, 2015, 2015 16th Latin-American Test Symposium (LATS).

Editorial for the Special Issue on Development of CMOS-MEMS/NEMS Devices

Jaume Segura, Jaume Verd, J. Verd, 2019, Micromachines.

A compact propagation delay model for deep-submicron CMOS gates including crosstalk

Jaume Segura, José Luis Rosselló, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

Víctor H. Champac, Jaume Segura, Hector Villacorta, 2016, J. Electron. Test..

THERMAL-AWARE DESIGN RULES FOR NANOMETER ICs

Ali Keshavarzi, Jaume Segura, Josep L. Rosselló, 2005 .

Single event transients generation in silicon devices with pulsed laser

Jaume Segura, Ivan de Paul, Franco N. Bandi, 2015, 2015 10th Spanish Conference on Electron Devices (CDE).

Parametric failures in CMOS ICs - a defect-based analysis

Ali Keshavarzi, Jaume Segura, Charles F. Hawkins, 2002, Proceedings. International Test Conference.

Electrical Circuit Analysis

Jaume Segura, Charles F. Hawkins, C. Hawkins, 2004 .

Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation

Jaume Segura, Gabriel Torrens, Sebastià A. Bota, 2011, 2011 Design, Automation & Test in Europe.

A compact gate-level energy and delay model of dynamic CMOS gates

Jaume Segura, José Luis Rosselló, Carol de Benito, 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

Test and Reliability: Partners in IC Manufacturing, Part 1

Jaume Segura, Charles F. Hawkins, C. Hawkins, 1999, IEEE Des. Test Comput..

Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells

Montserrat Nafría, Antonio Rubio, Jaume Segura, 2017, 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Integrated microelectromechanical systems in the More than Moore era

Jaume Segura, 2017, 2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

On-line current testing for a microprocessor based application with an off-chip sensor

T. Miller, Jaume Segura, Bartomeu Alorda, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

Analysis of fin height on FinFET SRAM cell hardening

Victor Champac, Jaume Segura, Sebastia Bota, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators

Jaume Segura, Sebastià A. Bota, Jaume Verd, 2018, Sensors.

Built-in dynamic current sensor circuit for digital VLSI CMOS testing

Miquel Roca, Jaume Segura, Antonio Rubio, 1994 .

A novel wavelet transform-based transient current analysis for fault detection and localization

Kaushik Roy, Swarup Bhunia, Jaume Segura, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Chardin: an off-chip transient current monitor with digital interface for production testing

Ali Keshavarzi, Jaume Segura, Bartomeu Alorda, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Víctor H. Champac, Jaume Segura, Hector Villacorta, 2015, Microelectron. J..

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Víctor H. Champac, Jaume Segura, Sebastià A. Bota, 2013, 2013 14th Latin American Test Workshop - LATW.

A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers

Jaume Segura, José Luis Rosselló, 2002, PATMOS.

Failure Mechanisms and Testing in Nanometer Technologies

Jaume Segura, Charles F. Hawkins, J. M. Soden, 2006 .

CMOS Basic Gates

Jaume Segura, Charles F. Hawkins, C. Hawkins, 2004 .

Compact Static Power Model of Complex CMOS Gates

Jaume Segura, José Luis Rosselló, Sebastià A. Bota, 2005, PATMOS.

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination

Jaume Segura, Gabriel Torrens, José Luis Rosselló, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

A compact model to identify delay faults due to crosstalk

Jaume Segura, José Luis Rosselló, 2006, Proceedings of the Design Automation & Test in Europe Conference.

CMOS Basic Circuits

Jaume Segura, Charles F. Hawkins, 2004 .

Temperature effects on circuit synchronism

Jaume Segura, Sebastian A. Bota, Josep L. Rossello, 2005, SPIE Microtechnologies.

Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers

Jaume Segura, José Luis Rosselló, J. Segura, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Fully CMOS Low-Cost Chaotic Neural Network

Vicent Canals, Jaume Segura, José Luis Rosselló, 2006, The 2006 IEEE International Joint Conference on Neural Network Proceedings.

An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation

Jaume Segura, Sebastià A. Bota, Xavier Gili, 2011, 2011 Design, Automation & Test in Europe.

Challenges in Nanometric Technology Scaling: Trends and Projections

Vivek De, Ali Keshavarzi, Jaume Segura, 2002, VTS.

An off-chip sensor circuit for on-line transient current testing

André Ivanov, Jaume Segura, Bartomeu Alorda, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

CMOS Testing at the End of the Roadmap: Challenges and Opportunities

Jaume Segura, 2006, DDECS.

8T vs. 6T SRAM cell radiation robustness: A comparative analysis

Jaume Segura, Gabriel Torrens, Sebastià A. Bota, 2011, Microelectron. Reliab..

Power-delay modeling of dynamic CMOS gates for circuit optimization

Jaume Segura, José Luis Rosselló, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

A built-in quiescent current monitor for CMOS VLSI circuits

Antonio Rubio, H. Casier, Joan Figueras, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs

Jaume Segura, Gabriel Torrens, Sebastià A. Bota, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Smart temperature sensor for thermal testing of cell-based ICs

Jaume Segura, José Luis Rosselló, Sebastià A. Bota, 2005, Design, Automation and Test in Europe.

CMOS Electronics: How It Works, How It Fails

Jaume Segura, Charles F. Hawkins, C. Hawkins, 2004 .

Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism

Ali Keshavarzi, Jaume Segura, José Luis Rosselló, 2004, 2004 International Conferce on Test.

GHz testing and its fuzzy targets

Jaume Segura, Charles F. Hawkins, 2002, Proceedings. International Test Conference.

Test and Reliability: Partners in IC Manufacturing, Part 2

Jaume Segura, Charles F. Hawkins, Jerry M. Soden, 1999, IEEE Des. Test Comput..

Cantilever NEMS relay-based SRAM devices for enhanced reliability

Jaume Segura, Gabriel Torrens, Sebastià A. Bota, 2017, 2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Low V/sub DD/ vs. delay: is it really a good correlation metric for nanometer ICs?

Jaume Segura, José Luis Rosselló, Sebastià A. Bota, 2006, 24th IEEE VLSI Test Symposium.

The anatomy of nanometer timing failures

Jaume Segura, Charles F. Hawkins, C. Hawkins, 2005, European Test Symposium (ETS'05).

Leakage Power Characterization Considering Process Variations

Jaume Segura, José Luis Rosselló, Sebastià A. Bota, 2006, PATMOS.

A non-intrusive built-in sensor for transient current testing of digital VLSI circuits

Jaume Segura, Sebastià A. Bota, Bartomeu Alorda, 2005, 11th IEEE International On-Line Testing Symposium.

Impact of Thermal Gradients on Clock Skew and Testing

Ali Keshavarzi, Jaume Segura, José Luis Rosselló, 2006, IEEE Design & Test of Computers.

Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions

Jaume Segura, Sebastià A. Bota, Xavier Gili, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analysis of radiation-hardening techniques for 6T SRAMs with structured layouts

Jaume Segura, Gabriel Torrens, Sebastia Bota, 2009, 2009 IEEE International Reliability Physics Symposium.

Memory State Transient Analysis (MSTA): A New Soft Error Rate Measurement Method for CMOS Memory Elements Based on Stochastic Analysis

Jaume Segura, Gabriel Torrens, Jaume Verd, 2015, IEEE Transactions on Nuclear Science.

Testing of Stuck-Open Faults in Nanometer Technologies

Víctor H. Champac, Jaume Segura, Charles F. Hawkins, 2012, IEEE Design & Test of Computers.

A modern look at the CMOS stuck-open fault

Chuck Hawkins, Victor Champac, Jaume Segura, 2009, 2009 10th Latin American Test Workshop.

Charge-based testing BIST for embedded memories

Jaume Segura, Bartomeu Alorda, Ivan de Paúl, 2007, IET Comput. Digit. Tech..

Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator

Jaume Segura, Sebastià A. Bota, Jaume Verd, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Using stochastic logic for efficient pattern recognition analysis

Vicent Canals, Jaume Segura, José Luis Rosselló, 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

Reliability analysis of small delay defects in vias located in signal paths

Chuck Hawkins, Victor Champac, Jaume Segura, 2010, 2010 11th Latin American Test Workshop.

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

Víctor H. Champac, Jaume Segura, Sebastià A. Bota, 2012, Microelectron. Reliab..

Alternate characterization technique for static random-access memory static noise margin determination

Rodrigo Picos, Jaume Segura, José Luis Merino, 2013, Int. J. Circuit Theory Appl..

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

Antonio Rubio, Jaume Segura, Charles F. Hawkins, 1996, J. Electron. Test..

Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs

Jaume Segura, José Luis Rosselló, Sebastià A. Bota, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

An Experimental Approach to Accurate Alpha-SER Modeling and Optimization Through Design Parameters in 6T SRAM Cells for Deep-Nanometer CMOS

Jaume Segura, Gabriel Torrens, Bartomeu Alorda, 2014, IEEE Transactions on Device and Materials Reliability.

Stuck-Open Fault Leakage and Testing in Nanometer Technologies

Víctor H. Champac, Jaume Segura, Charles F. Hawkins, 2009, 2009 27th IEEE VLSI Test Symposium.

Analytical modeling of glitch propagation in nanometer ICs

Jaume Segura, Sebastià A. Bota, Xavier Gili, 2011, Microtechnologies.

A BIST-based charge analysis for embedded memories

Vicent Canals, Jaume Segura, Bartomeu Alorda, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

A Two-Level Power-Grid Model for Transient Current Testing Evaluation

Vicent Canals, Jaume Segura, Bartomeu Alorda, 2004, J. Electron. Test..

Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories

Jaume Segura, Gabriel Torrens, Sebastià A. Bota, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

A fast concurrent power-thermal model for sub-100 nm digital ICs

Ali Keshavarzi, Vicent Canals, Jaume Segura, 2005, Design, Automation and Test in Europe.

Top-side pulsed laser induced single event upsets in highly-scaled SRAM devices

Jaume Segura, Gabriel Torrens, Jaume Verd, 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis

Jaume Segura, Josep L. Rosselló, 2002 .

Analytical modeling of Single Event Transients propagation in combinational logic gates

Jaume Segura, Xavier Gili, Sebastia A. Bota, 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.