Kenichi Okabe

On Fortified Corrugated Board

Kenichi Okabe, 1976 .

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

T. Miyashita, Naoyoshi Tamura, Masataka Kase, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

T. Miyashita, Masaki Yamabe, Tetsu Tanaka, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

Masataka Kase, T. Sugii, Sergey Pidin, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).