Ruzica Jevtic

发表

Triple-bit method for power estimation of nonlinear digital circuits in FPGAs

Carlos Carreras, Bojan Jovanovic, Ruzica Jevtic, 2010 .

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes

Carlos Carreras, Ruzica Jevtic, Juan A. López, 2014, J. Syst. Archit..

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator

Andreas Wiesbauer, Richard Gaggl, Luis Hernández, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A complete dynamic power estimation model for data-paths in FPGA DSP designs

Carlos Carreras, Ruzica Jevtic, 2012, Integr..

Power estimation of dividers implemented in FPGAs

Carlos Carreras, Bojan Jovanovic, Ruzica Jevtic, 2011, GLSVLSI '11.

System Integration of RISC-V Processors with FD-SOI

James C.Y. Dunn, Elad Alon, Philippe Flatresse, 2020 .

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices

Lauri Koskinen, Ruzica Jevtic, Marko Ylitolva, 2018, 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Technology Variability From a Design Perspective

Costas J. Spanos, B. Giraud, Kun Qian, 2011, IEEE Trans. Circuits Syst. I Regul. Pap..

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components

Domenik Helms, Carlos Carreras, Ruzica Jevtic, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

Switching Activity Models for Power Estimation in FPGA Multipliers

Gabriel Caffarena, Carlos Carreras, Ruzica Jevtic, 2007, ARC.

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

Matthew J. Turnquist, Lauri Koskinen, Ruzica Jevtic, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

Elad Alon, Borivoje Nikolic, Krste Asanovic, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits

Carlos Carreras, Bojan Jovanovic, Ruzica Jevtic, 2014, IEEE Transactions on Industrial Informatics.

Power Measurement Methodology for FPGA Devices

Carlos Carreras, Ruzica Jevtic, 2011, IEEE Transactions on Instrumentation and Measurement.

Floorplan-based FPGA interconnect power estimation in DSP circuits

Carlos Carreras, Ruzica Jevtic, Vukasin Pejovic, 2009, SLIP '09.

High-level power estimation of dsp circuits implemented in fpgas

Ruzica Jevtic, 2009 .

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

Elad Alon, Philippe Flatresse, Borivoje Nikolic, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Power Estimation of Embedded Multiplier Blocks in FPGAs

Carlos Carreras, Ruzica Jevtic, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

Elad Alon, Philippe Flatresse, Borivoje Nikolic, 2016, IEEE Journal of Solid-State Circuits.

An Agile Approach to Building RISC-V Microprocessors

David Patterson, Alberto Puggelli, Elad Alon, 2016, IEEE Micro.

Analytical High-Level Power Model for LUT-Based Components

Carlos Carreras, Ruzica Jevtic, 2008, PATMOS.

Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models

Gabriel Caffarena, Carlos Carreras, Ruzica Jevtic, 2008 .

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking

Elad Alon, Borivoje Nikolic, Krste Asanovic, 2015, 2015 IEEE Hot Chips 27 Symposium (HCS).

A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials

Abraham Otero, Madhav P. Desai, Gabriel Caffarena, 2021, Electronics.