Hiromi Inaba

发表

Parallel multiple electric power conversion system constructed by connecting three power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2013, 2013 International Conference on Electrical Machines and Systems (ICEMS).

Intelligent Control of Elevator System

Hiromi Inaba, 1993 .

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

Hidetoshi Onodera, Hiroshi Inoue, Akira Tsuchiya, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Highly Efficient Contactless Electrical Energy Transmission System.

Hiroshi Nagase, Hiromi Inaba, Hideki Ayano, 2003 .

Tail Cordless Elevator System

Hideki Ayano, Hiromi Inaba, Takashi Teramoto, 2003 .

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector

Hiroshi Inoue, Akira Tsuchiya, Kosuke Furuichi, 2016, 2016 International SoC Design Conference (ISOCC).

25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS

Akira Tsuchiya, Keiji Kishine, Hiromi Inaba, 2014, 2014 International SoC Design Conference (ISOCC).

Apparatus and method for controlling a power converter.

Hiromi Inaba, Mitsuyuki Hombu, Toshimitsu Tobita, 1987 .

A highly efficient contactless electrical energy transmission system

Hiroshi Nagase, Hiromi Inaba, Hideki Ayano, 2004 .

Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

Hidetoshi Onodera, Keiji Kishine, Hiromi Inaba, 2009 .

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS

Hiroshi Koizumi, Keiji Kishine, Makoto Nakamura, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops

Hidetoshi Onodera, Hiroshi Inoue, Akira Tsuchiya, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

System construction method of parallel operation system constructed with three electric power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2014, 2014 17th International Conference on Electrical Machines and Systems (ICEMS).

Method and apparatus for preventing traffic congestion in distributed network systems

Hiromi Inaba, Kiyoshi Nakamura, Junzo Kawakami, 1990 .

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS

Hideyuki Nosaka, Shinsuke Nakano, Masafumi Nogawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Analysis of parallel operation methods of PWM inverter sets for an ultra-high speed elevator

Hiromi Inaba, T. Yoshikawa, Toshisuke Mine, 2000, APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058).

A-1-19 Simplification of Labeling Signal Detecting Circuit Using a Delay Detection Circuit

Keiji Kishine, Hiromi Inaba, Tomoki Tanaka, 2016 .

Examination of cross current suppression method using control of parallel operation system constructed by two electric power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2014, 2014 17th International Conference on Electrical Machines and Systems (ICEMS).

A Control Method and An Output Voltage Stabilization Method for Matrix Converter Using Venturini Control Algorithm

Satoshi Ogasawara, Hideki Ayano, Hiromi Inaba, 2006 .

10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2018 .

Reduction Effect of EMI in Parallel Matrix Converter Systems

Satoshi Ogasawara, Hideki Ayano, Hiromi Inaba, 2008 .

An elevator characterized group supervisory control system

Hiromi Inaba, Toshimitsu Tobita, Atsuya Fujino, 1991, Proceedings IECON '91: 1991 International Conference on Industrial Electronics, Control and Instrumentation.

Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2017 .

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control

Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique

Keiji Kishine, Hiromi Inaba, Tomoki Tanaka, 2016 .

Cross current suppression control for parallel operation system constructed with two electric power converters under different output

Keiji Kishine, Hiromi Inaba, Keisuke Ishikura, 2016, 2016 19th International Conference on Electrical Machines and Systems (ICEMS).

Simulation analysis of control methods for parallel multi-operating system constructed by the same output power converters

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2013, 2013 International Conference on Electrical Machines and Systems (ICEMS).

Development of a high-speed elevator controlled by current source inverter system with sinusoidal input and output

Hiromi Inaba, M. Hombu, Takeki Ando, 1992 .

Study of three inputs combination reactor of parallel operation systems constructed with multiple electric power converters

Keiji Kishine, Hiromi Inaba, Keisuke Ishikura, 2015, 2015 18th International Conference on Electrical Machines and Systems (ICEMS).

Method controlling two or more sets of PMSM by one inverter on a railway vehicle

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2013, 2013 International Conference on Electrical Machines and Systems (ICEMS).

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2016, 2016 International SoC Design Conference (ISOCC).

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

Akira Tsuchiya, Keiji Kishine, Hiromi Inaba, 2016 .

Design method of cross current suppression control for parallel operation system constructed with two electric power converters

Keiji Kishine, Hiromi Inaba, Keisuke Ishikura, 2015, 2015 18th International Conference on Electrical Machines and Systems (ICEMS).

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2016, 2016 International SoC Design Conference (ISOCC).

Driving parameter survey and experiment on railway drive system by using two or more permanent magnet synchronous motors controlled using one inverter

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2015, 2015 18th International Conference on Electrical Machines and Systems (ICEMS).

Method controlling four sets of permanent magnet synchronous motor by one inverter on a railway vehicle

Keiji Kishine, Mitsuki Nakai, Hiromi Inaba, 2014, 2014 17th International Conference on Electrical Machines and Systems (ICEMS).

Simple and Low Power Highly Sensitive Frequency Demodulator Circuit for 10-Gb/s Transmission System for Labeling Signal

Hiromu Uemura, Keiji Kishine, Hiromi Inaba, 2017 .

A Parallel Matrix Converter System

Satoshi Ogasawara, Hideki Ayano, Hiromi Inaba, 2006 .