Erik Jan Marinissen

发表

Automated Probe-Mark Analysis for Advanced Probe Technology Characterization

Yu-Rong Jian, Ferenc Fodor, Cheng-Wen Wu, 2020 .

C. P. Ravikumar, Erik Jan Marinissen, Bashir M. Al-Hashimi, 2006, IEEE Design & Test of Computers.

Processing active devices on Si interposer and impact on cost

Eric Beyne, Erik Jan Marinissen, Mirko Scholz, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO

Erik Jan Marinissen, Paul Wielage, Michel Altheimer, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Robust Optimization of Test-Access Architectures Under Realistic Scenarios

Erik Jan Marinissen, Krishnendu Chakrabarty, Sergej Deutsch, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Redundancy modelling and array yield analysis for repairable embedded memories

Erik Jan Marinissen, Krishnendu Chakrabarty, Anuja Sehgal, 2005 .

On-chip test infrastructure design for optimal multi-site testing

Erik Jan Marinissen, Sandeep Kumar Goel, 2006 .

A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards

Ferenc Fodor, Erik Jan Marinissen, Bart De Wachter, 2017, 2017 International Test Conference in Asia (ITC-Asia).

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption

Erik Jan Marinissen, Urban Ingelsson, Erik Larsson, 2015, IEEE Transactions on Computers.

Creating options for 3D-SIC testing

Erik Jan Marinissen, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

3D integration: Circuit design, test, and reliability challenges

Paul Marchal, Erik Jan Marinissen, Dimitrios Velenis, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

Alexandre M. Amory, Fernando Gehm Moraes, Kees G. W. Goossens, 2007, IET Comput. Digit. Tech..

Cost comparison between 3D and 2.5D integration

Eric Beyne, Erik Jan Marinissen, Mikael Detalle, 2012, 2012 4th Electronic System-Integration Technology Conference.

Interconnect test for 3D stacked memory-on-logic

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base

Erik Jan Marinissen, Cheng-Wen Wu, Sandeep Kumar Goel, 2011, 2011 IEEE International Test Conference.

Test Resource Management and Scheduling for Modular Manufacturing Test of SOCs

Erik Jan Marinissen, Sandeep Kumar Goel, E. Marinissen, 2004 .

SOC test architecture design for efficient utilization of test bandwidth

Erik Jan Marinissen, Sandeep Kumar Goel, E. Marinissen, 2003, TODE.

DfT Architecture for 3D-SICs with Multiple Towers

Erik Jan Marinissen, Cheng-Wen Wu, Sandeep Kumar Goel, 2011, 2011 Sixteenth IEEE European Test Symposium.

Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2012, J. Electron. Test..

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits

Yu-Rong Jian, Ferenc Fodor, Erik Jan Marinissen, 2018, 2018 IEEE International Test Conference (ITC).

User-constrained test architecture design for modular SOC testing

Erik Jan Marinissen, Bruno Rouzeyre, Marie-Lise Flottes, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

“Our Original 3D Idea Still Has To Happen; And It Will”

Erik Jan Marinissen, 2013 .

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Erik Jan Marinissen, E. Marinissen, 2002, J. Electron. Test..

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis, 2010, 2010 15th IEEE European Test Symposium.

Cell-aware test: significant test quality improvement at affordable cost

Erik Jan Marinissen, Kees Goossens, Jos Huisken, 2018 .

A structured and scalable test access architecture for TSV-based 3D stacked ICs

Mario H. Konijnenburg, Erik Jan Marinissen, Jouke Verbree, 2010, 2010 28th VLSI Test Symposium (VTS).

Automated testing of bare die-to-die stacks

Teng Wang, Erik Jan Marinissen, Jens Fiedler, 2015, 2015 IEEE International Test Conference (ITC).

Application of Deterministic Logic BIST on Industrial Circuits

Gundolf Kiefer, Erik Jan Marinissen, Hans-Joachim Wunderlich, 2001, J. Electron. Test..

Message from the Program Chairs

Erik Jan Marinissen, 1997, IEEE Symposium on Security and Privacy.

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing

Erik Jan Marinissen, Maurice Lousberg, Tom Waayers, 2005, 14th Asian Test Symposium (ATS'05).

Efficient test access mechanism optimization for system-on-chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip

Erik Jan Marinissen, Sandeep Kumar Goel, Steven Oostdijk, 2004, DATE.

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

Kees G. W. Goossens, Erik Jan Marinissen, Georgi Gaydadjiev, 2010, J. Electron. Test..

Test-station for flexible semi-automatic wafer-level silicon photonics testing

Erik Jan Marinissen, Peter De Heyn, Joris Van Campenhout, 2016, 2016 21th IEEE European Test Symposium (ETS).

Electrical Modeling of STT-MRAM Defects

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2018, 2018 IEEE International Test Conference (ITC).

Silicon debug of systems-on-chips

Erik Jan Marinissen, Karel van Doorselaer, Sridhar Narayanan, 1998, DATE.

Automation of 3D-DfT Insertion

Mario H. Konijnenburg, Vivek Chickermane, Brion L. Keller, 2011, 2011 Asian Test Symposium.

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Mario H. Konijnenburg, Erik Jan Marinissen, Chun-Chuan Chi, 2012, J. Electron. Test..

Cluster-based test architecture design for system-on-chip

Erik Jan Marinissen, Sandeep Kumar Goel, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Imec's 3D-DfT Architecture: Basics, Extensions, and Demonstrator Results

Erik Jan Marinissen, Tobias Burgherr, 2011 .

On using IEEE P1500 SECT for test plug-n-play

Yervant Zorian, Rohit Kapur, Erik Jan Marinissen, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory

Yervant Zorian, Erik Jan Marinissen, 2017, IEEE Des. Test.

Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios

Ferenc Fodor, Erik Jan Marinissen, Michele Stucchi, 2020, 2020 IEEE European Test Symposium (ETS).

Test-architecture optimization for TSV-based 3D stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2010, 2010 15th IEEE European Test Symposium.

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism

Kees G. W. Goossens, Erik Jan Marinissen, Georgi Gaydadjiev, 2008, 2008 13th European Test Symposium.

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2012, 2012 IEEE International Test Conference.

Challenges in testing core-based system ICs

Yervant Zorian, Erik Jan Marinissen, Y. Zorian, 1999, IEEE Commun. Mag..

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs

Erik Jan Marinissen, Alkis A. Hatzopoulos, Hailong Jiao, 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Test scheduling for modular SOCs in an abort-on-fail environment

Erik Jan Marinissen, Urban Ingelsson, Erik Larsson, 2005, European Test Symposium (ETS'05).

Creating options for 3D-SIC testing

Erik Jan Marinissen, 2013, VLSI-DAT.

Infrastructure for modular SOC testing

Erik Jan Marinissen, Tom Waayers, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

DATE 07 workshop on diagnostic services in NoCs

Axel Jantsch, Erik Jan Marinissen, Nicola Nicolici, 2007, IEEE Des. Test Comput..

Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

Erik Jan Marinissen, Sandeep Kumar Goel, E. Marinissen, 2005 .

DATE 2009 Workshop on 3D Integration

Erik Jan Marinissen, Geert Van der Plas, Yann Guillou, 2009 .

A set of benchmarks for modular testing of SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings. International Test Conference.

Vesuvius-3D: A 3D-DfT demonstrator

Erik Jan Marinissen, Sergej Deutsch, Bart De Wachter, 2014, 2014 International Test Conference.

2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, VLSI-DAT.

Test protocol scheduling for embedded-core based system ICs

Erik Jan Marinissen, Joep Aerts, 1998 .

An Industrial Approach to Core-Based System Chip Testing

Erik Jan Marinissen, E. Marinissen, 2001, VLSI-SOC.

Testing embedded-core based system chips

Yervant Zorian, Sujit Dey, Erik Jan Marinissen, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Microelectronics and test in "The New Europe" - challenges and opportunities in research and industry

Erik Jan Marinissen, 2005 .

System chip test: how will it impact your design?

Yervant Zorian, Erik Jan Marinissen, 2000, Proceedings 37th Design Automation Conference.

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Effective and efficient test architecture design for SOCs

Erik Jan Marinissen, Sandeep Kumar Goel, E. Marinissen, 2002, Proceedings. International Test Conference.

Process Complexity and Cost Considerations of Multi-Layer Die Stacks

Eric Beyne, Erik Jan Marinissen, Geert Van der Plas, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Erik Jan Marinissen, Erik Larsson, Paul Wielage, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Bugs, moths, grasshoppers, and whales

Erik Jan Marinissen, 2008, IEEE Design & Test of Computers.

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing

Erik Jan Marinissen, Ozgur Sinanoglu, Jeff Rearick, 2009, IEEE Design & Test of Computers.

Optimal Interconnect ATPG Under a Ground-Bounce Constraint

Erik Jan Marinissen, Henk D. L. Hollmann, Bart Vermeulen, 2005, J. Electron. Test..

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects

Friedrich Hapke, Erik Jan Marinissen, Andreas Glowatz, 2007, 2007 IEEE International Test Conference.

Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Efficient Wrapper/TAM co-optimization for large SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests pdf

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2020, ArXiv.

3D DfT architecture for pre-bond and post-bond testing

Mario H. Konijnenburg, Erik Jan Marinissen, Chun-Chuan Chi, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Mr. Synopsys Speaks: The Aart of Tech-Onomic Orchestration of Adjacent Version $n+1$

Erik Jan Marinissen, 2014 .

High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO

Erik G. Larsson, Erik Jan Marinissen, Paul Wielage, 2006 .

Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis

Erik Jan Marinissen, Robert C. Aitken, 2008, IEEE Des. Test Comput..

Testing TSV-based three-dimensional stacked ICs

Erik Jan Marinissen, E. Marinissen, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits

Yervant Zorian, Erik Jan Marinissen, 2012, J. Electron. Test..

Control-aware test architecture design for modular SOC testing

Erik Jan Marinissen, Sandeep Kumar Goel, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2009, IEEE Transactions on Computers.

Pioneering in Asia With the US Venture Capital Model

Erik Jan Marinissen, 2012, IEEE Des. Test Comput..

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2014, 2014 International Test Conference.

Session details: Advances in design-for-testability methods

Erik Jan Marinissen, Patrick Girard, Tom Williams, 2005, DAC '05.

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2010, 2010 IEEE International Test Conference.

Defect-Location Identification for Cell-Aware Test

Kees G. W. Goossens, Erik Jan Marinissen, Zhan Gao, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Testing 3D Stacked ICs Containing Through-Silicon Vias

Erik Jan Marinissen, 2011, 3D Integration for NoC-based SoC Architectures.

Design issues in heterogeneous 3D/2.5D integration

Diederik Verkest, Eric Beyne, Paul Marchal, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

EmbeddedMulti-DetectATPG andItsEffectontheDetectionofUnmodeledDefects

Friedrich Hapke, Erik Jan Marinissen, Andreas Glowatz, 2007 .

Recent advances in test planning for modular testing of core-based SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Towards a standard for embedded core test: an example

Yervant Zorian, Rohit Kapur, Erik Jan Marinissen, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Security vs. test quality: can we really only have one at a time?

Erik Jan Marinissen, 2004, 2004 International Conferce on Test.

IEEE P1500-compliant test wrapper design for hierarchical cores

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2004, 2004 International Conferce on Test.

EDA solutions to new-defect detection in advanced process technologies

Friedrich Hapke, Erik Jan Marinissen, Sandeep Kumar Goel, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Application of deterministic logic BIST on industrial circuits

Gundolf Kiefer, Erik Jan Marinissen, Hans-Joachim Wunderlich, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Active-lite interposer for 2.5 & 3D integration

Eric Beyne, Erik Jan Marinissen, Mirko Scholz, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Deterministic Scan-Chain Diagnosis for Intermittent Faults

Erik Jan Marinissen, Erik G. Larsson, Dan Adolfsson, 2009, ETS 2009.

Evaluation of TSV and micro-bump probing for wide I/O testing

Erik Jan Marinissen, Eric Strid, Ken Smith, 2011, 2011 IEEE International Test Conference.

Wrapper design for embedded core test

Yervant Zorian, Erik Jan Marinissen, Sandeep Kumar Goel, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices

Erik Jan Marinissen, Kees Goossens, Min-Chun Hu, 2019, 2019 IEEE International Test Conference in Asia (ITC-Asia).

Reflow process optimization for micro-bumps applications in 3D technology

Eric Beyne, Erik Jan Marinissen, Andy Miller, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

A process for the memory test

Erik Jan Marinissen, Paul Wielage, Guillaume E. A. Lousberg, 2000 .

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Brandon Noia, 2010, 2010 IEEE International Test Conference.

Testing of 3D Chips: Is There Anything New Under the Sun?

Erik Jan Marinissen, Michael Laisne, Kenneth Parker, 2009 .

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2020, 2020 IEEE International Test Conference (ITC).

Quality versus cost analysis for 3D Stacked ICs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Using 3D-COSTAR for 2.5D test cost optimization

Erik Jan Marinissen, Said Hamdioui, Sudipta Bhawmik, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

3D design‐for‐test architecture

Mario Konijnenburg, Vivek Chickermane, Erik Jan Marinissen, 2019 .

IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs

Erik Jan Marinissen, Hailong Jiao, Teresa L. McLaurin, 2016, 2016 21th IEEE European Test Symposium (ETS).

Cost Modeling for 2.5D and 3D Stacked ICs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2019 .

Challenges in Testing

Erik Jan Marinissen, 1999 .

Impact of mid-bond testing in 3D stacked ICs

Erik Jan Marinissen, Said Hamdioui, Sudipta Bhawmik, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Trends in testing integrated circuits

Camelia Hora, Erik Jan Marinissen, Bram Kruseman, 2004, 2004 International Conferce on Test.

Improved Scan Chain Diagnosis

Erik Jan Marinissen, Erik G. Larsson, Dan Adolfsson, 2007 .

Murphy goes 3D

Erik Jan Marinissen, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Test Cost Analysis for 3D Die-to-Wafer Stacking

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2010, 2010 19th IEEE Asian Test Symposium.

Test challenges for 3D-SICs: All the old, most of the recent, and then some new!

Erik Jan Marinissen, 2009 .

Testing Embedded-Core-Based System Chips

Yervant Zorian, Sujit Dey, Erik Jan Marinissen, 1999, Computer.

Yield analysis for repairable embedded memories

Erik Jan Marinissen, Krishnendu Chakrabarty, Anuja Sehgal, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

Defect and Fault Modeling Framework for STT-MRAM Testing

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2021, IEEE Transactions on Emerging Topics in Computing.

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

Alexandre M. Amory, Fernando Gehm Moraes, Kees G. W. Goossens, 2006, Eleventh IEEE European Test Symposium (ETS'06).

Guest Editors' Introduction: Robust 3-D Stacked ICs

Erik Jan Marinissen, Pascal Vivet, Fabian Hopsch, 2016, IEEE Des. Test.

Optimal interconnect atpg under a ground-flounce constraint

Erik Jan Marinissen, Henk D. L. Hollmann, Bart Vermeulen, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2015, TODE.

Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library

Kees G. W. Goossens, Erik Jan Marinissen, Min-Chun Hu, 2019, 2019 IEEE International Test Conference (ITC).

Challenges in embedded memory design and test

Erik Jan Marinissen, Doris Keitel-Schulz, Yervant Zorian, 2005, Design, Automation and Test in Europe.

Creating value through test

Erik Jan Marinissen, Bart Vermeulen, Michael Müller, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Device-Aware Test: A New Test Approach Towards DPPB Level

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2019, 2019 IEEE International Test Conference (ITC).

Trends in testing integrated circuits

Erik Jan Marinissen, C. Hora, Bart Vermeulen, 2004 .

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, J. Electron. Test..

Cost components for 3D system integration

Eric Beyne, Erik Jan Marinissen, Anne Jourdain, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base

Erik Jan Marinissen, Cheng-Wen Wu, Sandeep Kumar Goel, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Adapting to adaptive testing

Kenneth M. Butler, Erik Jan Marinissen, Adit D. Singh, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study

Vivek Chickermane, Erik Jan Marinissen, Sandeep Kumar Goel, 2019 .

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base

Erik Jan Marinissen, Cheng-Wen Wu, Sandeep Kumar Goel, 2011, 2011 Asian Test Symposium.

On IEEE P1500's Standard for Embedded Core Test

Yervant Zorian, Rohit Kapur, Erik Jan Marinissen, 2002, J. Electron. Test..

IEEE P1500-compliant test wrapper design for hierarchical cores

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2004 .

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2019, 2019 IEEE European Test Symposium (ETS).

Cost effectiveness of 3D integration options

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

3D test: no longer a bottleneck!

Erik Jan Marinissen, 2019 .

Editorial Silicon Debug and Diagnosis

Erik Jan Marinissen, Nicola Nicolici, 2007, IET Comput. Digit. Tech..

Layout-driven SOC test architecture design for test time and wire length minimization

Erik Jan Marinissen, Sandeep Kumar Goel, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

Erik Jan Marinissen, Sandeep Kumar Goel, E. Marinissen, 2003, J. Electron. Test..

Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2

Yervant Zorian, Erik Jan Marinissen, 2009, IEEE Des. Test Comput..

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing

Erik Jan Marinissen, Ozgur Sinanoglu, 2008, 2008 Design, Automation and Test in Europe.

How significant will be the test cost share for 3D die-to-wafer stacked-ICs?

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Ming Shao, Erik Jan Marinissen, Yu Li, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access

Erik Jan Marinissen, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

On using rectangle packing for SOC wrapper/TAM co-optimization

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

IEEE Std P1838: 3D test access standard under development

Erik Jan Marinissen, Sandeep Kumar Goel, Adam Cron, 2019 .

Editorial

Erik Jan Marinissen, Christian Landrault, 2007, IET Comput. Digit. Tech..

Automatic Generation of In-Circuit Tests for Board Assembly Defects

Erik Jan Marinissen, Harm van Schaaijk, Martien Spierings, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

On modeling and optimizing cost in 3D Stacked-ICs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).

Impact of 3D design choices on manufacturing cost

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2009, 2009 IEEE International Conference on 3D System Integration.

Industry collaboration in 3-D IC tools

Erik Jan Marinissen, Dragomir Milojevic, Geert Van der Plas, 2012 .

Embedded toggle generator to provide realistic test conditions during test of digital 2D-SoCs and 3D-SICs

Erik Jan Marinissen, Alkis A. Hatzopoulos, Christos Papameletis, 2018 .

How Useful are the ITC 02 SoC Test Benchmarks?

Erik Jan Marinissen, Krishnendu Chakrabarty, 2002, IEEE Des. Test Comput..

Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Sergej Deutsch, 2013, 2013 IEEE International Test Conference (ITC).

Si interposer build-up options and impact on 3D system cost

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

IEEE Std 1500 Enables Modular SoC Testing

Yervant Zorian, Erik Jan Marinissen, 2009, IEEE Design & Test of Computers.

Developing silicon photonics technologies with a wafer-level test station

Erik Jan Marinissen, Joris Van Campenhout, Jeroen De Coster, 2018 .

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2013, 2013 18th IEEE European Test Symposium (ETS).

Will Test Compression Run Out of Gas

Erik Jan Marinissen, S. K. Goel, 2008 .

Minimizing pattern count for interconnect test under a ground bounce constraint

Erik Jan Marinissen, Henk D. L. Hollmann, Ben Bennetts, 2003, IEEE Design & Test of Computers.

On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs

Erik Jan Marinissen, Alkis A. Hatzopoulos, Hailong Jiao, 2018, 2018 IEEE International Test Conference (ITC).

On Scan Chain Diagnosis for Intermittent Faults

Erik Jan Marinissen, Erik Larsson, Dan Adolfsson, 2009, 2009 Asian Test Symposium.

Impact of Magnetic Coupling and Density on STT-MRAM Performance

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Testing 3D chips containing through-silicon vias

Yervant Zorian, Erik Jan Marinissen, Y. Zorian, 2009, 2009 International Test Conference.

IoT: Source of test challenges

Mario Konijnenburg, Yervant Zorian, Erik Jan Marinissen, 2016, 2016 21th IEEE European Test Symposium (ETS).

Guest Editors' Introduction: The Status of IEEE Std 1500

Yervant Zorian, Erik Jan Marinissen, 2009, IEEE Des. Test Comput..

Zero Defect: Mission Impossible?

Erik Jan Marinissen, Sandeep Kumar Goel, 2006 .

On-chip test infrastructure design for optimal multi-site testing of system chips

Erik Jan Marinissen, Sandeep Kumar Goel, 2005, Design, Automation and Test in Europe.

Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Brandon Noia, 2012, J. Electron. Test..

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2021 .

Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores

Yervant Zorian, Erik Jan Marinissen, G. Giles, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Optimization of Test‐Access Architectures and Test Scheduling for 3D ICs

Erik Jan Marinissen, Sergej Deutsch, Brandon Noia, 2019 .

Pre‐bond testing through direct probing of large‐array fine‐pitch micro‐bumps

Erik Jan Marinissen, Bart De Wachter, Jorg Kiesewetter, 2019 .

Contactless testing: Possibility or pipe-dream?

John P. Hayes, Erik Jan Marinissen, Laurence Pujol, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Automatic generation of in-circuit tests for board assembly defects

Erik Jan Marinissen, Harm van Schaaijk, Martien Spierings, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults

Erik Jan Marinissen, Kees Goossens, Min-Chun Hu, 2020, 2020 IEEE European Test Symposium (ETS).

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Erik Jan Marinissen, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A structured and scalable mechanism for test access to embedded reusable cores

Erik Jan Marinissen, Clemens Wouters, Maurice Lousberg, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2003, IEEE Trans. Computers.

Automated Probe-Mark Analysis

Ferenc Fodor, Erik Jan Marinissen, Cheng-Wen Wu, 2018 .

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, DAC '02.

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

Erik Jan Marinissen, Hailong Jiao, Xugang Cao, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2021, IEEE Transactions on Computers.

IEEE Standard 1838 Is on the Move

Erik Jan Marinissen, Adam Cron, Riccardo Mariani, 2021, Computer.

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Kees G. W. Goossens, Erik Jan Marinissen, Jos Huisken, 2021, J. Electron. Test..

Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring

Erik Jan Marinissen, Makoto Nagata, Alkis A. Hatzopoulos, 2021, 2021 IEEE European Test Symposium (ETS).

Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis

Erik Jan Marinissen, Joe Swenton, Santosh Malagi, 2021, 2021 IEEE European Test Symposium (ETS).

Handbook of 3D Integration

Erik Jan Marinissen, Paul D. Franzon, Muhannad S. Bakir, 2019 .

NiB Capping of Cu landing pads for thermocompression bonding

Erik Jan Marinissen, Joeri De Vos, Luke England, 2014 .

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers

Vivek Chickermane, Brion L. Keller, Erik Jan Marinissen, 2015, IEEE Design & Test.

Wrapper Design for the Reuse of Functional Interconnect for Test

Alexandre M. Amory, Erik Jan Marinissen, Marcelo Lubaszewski, .