B. Swinnen

发表

3D technologies: Requiring more than 3 dimensions from concept to product

B. Swinnen, 2009, 2009 IEEE International Interconnect Technology Conference.

Through-silicon via technology for three-dimensional integrated circuit manufacturing

E. Beyne, K. Croes, P. Jaenen, 2012, 2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 International Electron Devices Meeting.

Underfill material screening and process characterization for 3D stacking

E. Beyne, Andy Miller, C. Gerets, 2012, 2012 4th Electronic System-Integration Technology Conference.

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

E. Beyne, K. Croes, A. Redolfi, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies

E. Beyne, I. De Wolf, A. Ivankovic, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Reliability concerns in copper TSV's: Methods and results

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies

E. Beyne, B. Vandevelde, B. Swinnen, 2008, EuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 Symposium on VLSI Technology.

Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology

E. Beyne, G. Eneman, P. Verheyen, 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

Integration of the ZoneBOND™ temporary bonding material in backside processing for 3D applications

E. Beyne, A. Jourdain, A. La Manna, 2012, 2012 4th Electronic System-Integration Technology Conference.

Influence of Extreme Thinning on 130-nm Standard CMOS Devices for 3-D Integration

C. Van Hoof, P. De Moor, K. De Munck, 2008, IEEE Electron Device Letters.

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

E. Beyne, A. Jourdain, S. Suhard, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

P. Soussan, E. Beyne, C. Huyghebaert, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Through-Si-Via Technology Solutions for 3D System Integration

Paresh Limaye, Eric Beyne, Anne Jourdain, 2009 .

Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture

E. Beyne, G. Eneman, S. Stoukatch, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration

Chris Van Hoof, Lieve Bogaerts, Jan Vaes, 2006 .

Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).