V. Kripesh

发表

Bed of nails - 100 microns pitch wafer level interconnections process

Vempati Srinivasa Rao, A.A.O. Tay, V. Kripesh, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

V. Kripesh, Seung Wook Yoon, A.G.K. Viswanath, 2008, IEEE Transactions on Advanced Packaging.

Link simulation of four channel CWDM transceiver modules

V. Kripesh, A. Priyadarshi, P.V. Ramana, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

Parametric design and solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

D. Pinjala, M.K. Iyer, Xiaowu Zhang, 2005, 2005 7th Electronic Packaging Technology Conference.

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

V. Kripesh, Seung Wook Yoon, A.G.K. Viswanath, 2008, IEEE Transactions on Advanced Packaging.

Bed of nails: fine pitch wafer-level packaging interconnects for high performance nano devices

A.A.O. Tay, Vempati Srinivasa Rao, V. Kripesh, 2005, 2005 7th Electronic Packaging Technology Conference.

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

A.A.O. Tay, V. Kripesh, S.S. Ang, 2006, IEEE Transactions on Advanced Packaging.

Development of 3-D Silicon Module With TSV for System in Packaging

Xiaowu Zhang, V. Kripesh, N. Khan, 2010, IEEE Transactions on Components and Packaging Technologies.

Development of 25-$\mu{\rm m}$ -Pitch Microbumps for 3-D Chip Stacking

A. Kumar, V. Kripesh, Aibin Yu, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Next generation of 100-/spl mu/m-pitch wafer-level packaging and assembly for systems-on-package

R.R. Tummala, C.P. Wong, M.K. Iyer, 2004, IEEE Transactions on Advanced Packaging.

Chip-last Embedded Active for System-On-Package (SOP)

R.R. Tummala, V. Kripesh, Baik-Woo Lee, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

A Novel Test Strategy for Fine Pitch Wafer-Level Packaged Devices

M.K. Iyer, Ban-Leong Ooi, A.A.O. Tay, 2007, IEEE Transactions on Advanced Packaging.

Simulation of forces acting on tiny chips during fluidic self-assembly

A.A.O. Tay, V. Kripesh, Hua Li, 2006, 2006 8th Electronics Packaging Technology Conference.

Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

V. Kripesh, Seung Wook Yoon, V.P. Ganesh, 2008, IEEE Transactions on Advanced Packaging.

Design and development of a multi-die embedded micro wafer level package

A. Kumar, V. Kripesh, Zhang Xiaowu, 2008, 2008 58th Electronic Components and Technology Conference.

Effect of wafer back grinding on the mechanical behavior of multilayered low-k for 3D-stack packaging applications

A. Kumar, V. Kripesh, Lu Shen, 2008, 2008 58th Electronic Components and Technology Conference.

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

V. Kripesh, Seung Wook Yoon, Hnin Wai Yin, 2008, 2008 10th Electronics Packaging Technology Conference.

Process Development and Reliability of Microbumps

V. Kripesh, J. Lau, Hnin Wai Yin, 2008, 2008 10th Electronics Packaging Technology Conference.

Refractive indices variation with temperature and humidity of optical adhesive

R. Rajoo, V. Kripesh, A. Priyadarshi, 2005 .

Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor

A. Kumar, V. Kripesh, G. Meyer-Berg, 2008, 2008 10th Electronics Packaging Technology Conference.

Optical coupling efficiency studies of passively aligned CWDM optical modules

Anand Asundi, Qingxin Zhang, V. Kripesh, 2005 .

Single-wall carbon nanotube (SWCNT) functionalized Sn–Ag–Cu lead-free composite solders

V. Kripesh, Andrew A. O. Tay, V. Kripesh, 2008 .

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

A. Kumar, D. Pinjala, J. H. Lau, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

John H. Lau, V. Kripesh, Shiguo Liu, 2009, 2009 59th Electronic Components and Technology Conference.

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

A. Kumar, V. Kripesh, Aibin Yu, 2008, 2008 10th Electronics Packaging Technology Conference.

Three-dimensional system-in-package using stacked silicon platform technology

V. Kripesh, N. Khan, V.P. Ganesh, 2005, IEEE Transactions on Advanced Packaging.

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

V. Kripesh, N. Balasubramanian, O.K. Navas, 2009, IEEE Transactions on Advanced Packaging.

Self-Assembly of Components using Shape-matching

V. Kripesh, E.B. Liao, Y.Y. Ong, 2007, 2007 9th Electronics Packaging Technology Conference.

High performance embedded RF passive device process integration

V. Kripesh, N. Khan, E.B. Liao, 2008, 2008 58th Electronic Components and Technology Conference.

Dry Self-Assembly & Gang bonding of micro-components from silicon carrier to substrate wafer

V. Kripesh, E.B. Liao, Y.Y. Ong, 2006, 2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium.

Optimization of the Thermomechanical Reliability of a 65 nm Cu/Low-$k$ Large-Die Flip Chip Package

V. Kripesh, X. Zhang, A.A.O. Tay, 2009, IEEE Transactions on Components and Packaging Technologies.

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

D. Pinjala, V. Kripesh, Seung Wook Yoon, 2009, IEEE Transactions on Components and Packaging Technologies.

Cu via Exposure by Backgrinding for TSV Applications

V. Kripesh, N. Khan, W.S.V. Lee, 2007, 2007 9th Electronics Packaging Technology Conference.

Sub-modeling technique for thermo-mechanical simulation of solder microbumps assembly in 3D chip stacking

Dim-Lee Kwong, V. Kripesh, Aibin Yu, 2009, 2009 11th Electronics Packaging Technology Conference.

UBM integrity studies on copper/low-k dielectrics for fine pitch flip chip packaging

M. K. Iyer, V. Kripesh, Seung Wook Yoon, 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-k Stack

A. Kumar, J. H. Lau, V. Kripesh, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device

Ying Ying Lim, V. Kripesh, Andy Fenner, 2010, 2010 12th Electronics Packaging Technology Conference.

Through wafer copper via for silicon based SiP application

V. Kripesh, Seung Wook Yoon, D. Witarsa, 2005, 2005 7th Electronic Packaging Technology Conference.

3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections

D. Pinjala, J. H. Lau, V. Kripesh, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Direct liquid cooling of a stacked MCM

D. Pinjala, V. Kripesh, Hengyun Zhang, 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).