B.L. Ji

Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications

B.L. Ji, S. Munetoh, Chorng-Lii Hwang, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

Operational amplifier based test structure for transistor threshold voltage variation

M.B. Ketchen, B.L. Ji, D.J. Pearson, 2008, 2008 IEEE International Conference on Microelectronic Test Structures.

Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

M.B. Ketchen, B.L. Ji, D.J. Pearson, 2009, IEEE Transactions on Semiconductor Manufacturing.

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization

B.L. Ji, P. Murfet, H. Ainspan, 2005, IEEE Journal of Solid-State Circuits.

On the Connection of SRAM Cell Stability with Switching History in Partially Depleted SOI Technology

M.B. Ketchen, H.I. Hanafi, B.L. Ji, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.