Mudit Bhargava

发表

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS

Ken Mai, Cagla Cakir, Mudit Bhargava, 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling pdf

Shidhartha Das, Saurabh Sinha, Brian Cline, 2020, ArXiv.

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS

Ken Mai, Cagla Cakir, Mudit Bhargava, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms

Cagla Cakir, Mudit Bhargava, Andy W Chen, 2019, 2019 Symposium on VLSI Circuits.

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators

H.-S. Philip Wong, Paul N. Whatmough, Mudit Bhargava, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

Benton H. Calhoun, Ken Mai, Mudit Bhargava, 2009, 2009 IEEE International Conference on Computer Design.

Low-overhead, digital offset compensated, SRAM sense amplifiers

Ken Mai, Mudit Bhargava, Mark P. McCartney, 2009, 2009 IEEE Custom Integrated Circuits Conference.

6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS

Ken Mai, Cagla Cakir, Mudit Bhargava, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement

Ken Mai, Mudit Bhargava, 2013, CHES.

Deeply hardware-entangled reconfigurable logic and interconnect

Ken Mai, Mudit Bhargava, Burak Erbagci, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only)

Ken Mai, Yu Cai, Erich F. Haratsch, 2011, FPGA '11.

Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor

Saurabh Sinha, Xiaoqing Xu, Brian Cline, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Reliable, Secure, Efficient Physical Unclonable Functions

Mudit Bhargava, M. Bhargava, 2013 .

Stylometric Analysis for Authorship Attribution on Twitter

Mudit Bhargava, Pulkit Mehndiratta, Krishna Asawa, 2013, BDA.

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

Umut Arslan, Lawrence T. Pileggi, Ken Mai, 2008, 2008 IEEE Custom Integrated Circuits Conference.

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Ken Mai, Mudit Bhargava, K. Mai, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC

Babak Falsafi, Ken Mai, Jangwoo Kim, 2013, 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing.

Side-channel attack resistant ROM-based AES S-Box

Ken Mai, Mudit Bhargava, Craig Teegarden, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Secure hardware-entangled field programmable gate arrays

Mudit Bhargava, Nail Etkin Can Akkaya, Burak Erbagci, 2019, J. Parallel Distributed Comput..

Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses

Ken Mai, Cagla Cakir, Mudit Bhargava, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Virtual prototyper (ViPro): An early design space exploration and optimization tool for SRAM designers

Benton H. Calhoun, Ken Mai, Mudit Bhargava, 2010, Design Automation Conference.

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states

Ken Mai, R. D. Blanton, Mudit Bhargava, 2013, 2013 IEEE International Test Conference (ITC).

Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers

Ken Mai, Kaship Sheikh, Mudit Bhargava, 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques

Mudit Bhargava, Martin Kinkade, Gus Yeung, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A Compact Model for Scalable MTJ Simulation pdf

Pranay Prabhat, Cyrille Dray, Mudit Bhargava, 2021, ArXiv.

A Fokker-Planck Solver to Model MTJ Stochasticity

Pranay Prabhat, Mudit Bhargava, Fernando Garc'ia-Redondo, 2021, ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).