Yong-Suk Joo

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Young-Jung Choi, Ki-Won Lee, Woo-Young Lee, 2007, IEEE Journal of Solid-State Circuits.

Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface

Young-Jung Choi, Woo-Young Lee, Jong-Ho Kang, 2009, 2009 Symposium on VLSI Circuits.