P.B. Moran

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Young-Jung Choi, Ki-Won Lee, Woo-Young Lee, 2007, IEEE Journal of Solid-State Circuits.

Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications

Bong-Seok Han, Min-Ho Kim, Jun-Ho Lee, 2006, 2006 IEEE Asian Solid-State Circuits Conference.