Nadine Azemard

发表

Request-skip adders : CMOS standard cell data dependent adders

Philippe Maurine, Robin Perrot, Nadine Azemard, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Library Free Integrated Circuits for Submicron Technologies

Daniel Auvergne, Jordi Carrabina, Nadine Azemard, 2002 .

SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2008 .

Circuit Sizing Methodunder DelayConstraint

Philippe Maurine, Nadine Azemard, Alexandre Verle, 2006 .

Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation

Daniel Auvergne, Nadine Azemard, Michel Aline, 1999 .

Library free integrated circuit design for submicron technologies

Daniel Auvergne, Fernando Moraes, Jordi Carrabina, 2000 .

A New Tool for Path Performance Optimization

Daniel Auvergne, Nadine Azemard, Michel Aline, 1998 .

Optimization Protocol Based on Performance Metric

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2004 .

POPS: Performance Optimization by Path Selection

Daniel Auvergne, Nadine Azemard, Michel Aline, 1998 .

Timing Performance Representation of a CMOS Standard Cell Library

Philippe Maurine, Daniel Auvergne, Sylvain Engels, 2003 .

Path Sensitization for Performance Optimization

Daniel Auvergne, Nadine Azemard, Jose Luis Guntzel, 1997 .

Delay-bound determination for path constraint satisfaction

Daniel Auvergne, Nadine Azemard, Michel Aline, 2000, Other Conferences.

Satisfaction of Delay/Power Constraints by Iterative Gate Sizing

Daniel Auvergne, Nadine Azemard, Michel Aline, 1999 .

Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

Statistical Energy Study for 28nm FDSOI Technology

Nadine Azemard, Gilles R. Ducharme, Rida Kheirallah, 2015 .

Local Gate Resizing for Critical Path Optimization

Daniel Auvergne, Nadine Azemard, Michel Aline, 1999 .

Perfornance Evaluation for Submicron CMOS Design

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

A Physical Synthesis Design Flow based on Virtual Components

Michel Robert, Daniel Auvergne, Fernando Moraes, 2000 .

Metric Definition for Buffer Insertion

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2002 .

A Path Selection Algorithm for Performance Optimization

Daniel Auvergne, Nadine Azemard, Jose Luis Guntzel, 1996 .

Upper and Lower bound Determination of delay on Critical Path

Daniel Auvergne, Nadine Azemard, Michel Aline, 2000 .

General representation of CMOS structure transition time for timing library representation

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2002 .

SmartVista: Smart Autonomous Multi Modal Sensors for Vital Signs Monitoring

Yan Zhang, Peter Ramm, Armin Klumpp, 2019 .

Integration, the VLSI Journal

Johan Vounckx, Philippe Maurine, Nadine Azemard, 2008 .

Evaluation of VLSI Layout Implementation for Efficiency

Michel Robert, Daniel Auvergne, Guy Cathébras, 1991 .

A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation

Michel Robert, Daniel Auvergne, Guy Cathébras, 1993 .

Conditional Moments based SSTA Considering Switching Process Induced Correlations

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2008 .

Automatic Layout Synthesis Based Performance Optimization

Philippe Maurine, Michel Robert, Daniel Auvergne, 2004 .

Selective Gate Sizing for Delay/Power Performance Management

Daniel Auvergne, Nadine Azemard, Séverine Cremoux, 1997 .

Path Selection Based on Incremental Technique

Daniel Auvergne, Nadine Azemard, Séverine Cremoux, 1998 .

Long and Short Path Sizing for Delay-Power Performance Management

Daniel Auvergne, Nadine Azemard, Séverine Cremoux, 1998 .

Technological Assignment for a Minimal Power Consumption

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

On-Chip Process Variability Monitoring

Philippe Maurine, Sylvain Engels, Robin Wilson, 2009 .

Spécial Issue in Journal of Low Power Electronics

Nadine Azemard, 2012 .

Ripple Carry Adder for Micropipeline Circuits

Philippe Maurine, Robin Perrot, Nadine Azemard, 2005 .

A Path Sensitization Approach for Performance Optimization

Daniel Auvergne, Nadine Azemard, Séverine Cremoux, 1997 .

Towards Autonomous Scalable Integrated Systems

Fabien Clermidy, Pascal Benoit, Lionel Torres, 2012 .

Optimization Protocol Based on Low Power Metrics

Philippe Maurine, Nadine Azemard, Alexandre Verle, 2005 .

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

RC on-chip interconnect Performance revisited

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2004 .

SSTA with Cell-to-Cell Delay Correlations

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2010 .

Design and Sizing of Tapered Buffers for Minimum Power-Delay Product

Daniel Auvergne, Nadine Azemard, Sandra Turgis, 1995 .

Circuit Performance Optimization under Delay Constraints

Philippe Maurine, Nadine Azemard, Alexandre Verle, 2006 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, France, ... (Lecture Notes in Computer Science)

Johan Vounckx, Philippe Maurine, Nadine Azemard, 2006 .

Timing Closure Management based on Delay Bound Determination

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

Sixteenth International Workshop on Power and Timing Modeling, Optimization and Simulation

Serge Pravossoudovitch, Johan Vounckx, Pascal Nouet, 2006 .

Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic Computing

Bernabe Linares-Barranco, Teresa Serrano-Gotarredona, Nadine Azemard, 2020 .

Voltage scaling and body biasing methodology for high performance hardwired LDPC

Robin Wilson, Philippe Maurine, Sylvain Engels, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Evaluation Dynamique et Optimisation des Structures CMOS et VLSI

Michel Robert, Daniel Auvergne, Nadine Azemard, 1989 .

Delay Bound Determination for Timing Closure on CMOS Circuits

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings

Lars Svensson, Nadine Azemard, 2007, PATMOS.

Special Issue: Power and Timing Modeling, Optimization and Simulation

Lars Svensson, Nadine Azemard, 2009 .

A Central Market Place for Dissemination of Low Power Microelectronics Design Knowledge

Daniel Auvergne, Patrick Girard, Nadine Azemard, 2003 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings

Johan Vounckx, Philippe Maurine, Nadine Azemard, 2006, PATMOS.

Statistical energy study for 28nm FDSOI devices

Gilles Ducharme, Jean-Marc Galliere, Nadine Azemard, 2015, 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

Energy study for 28nm FDSOI technology

Gilles Ducharme, Nadine Azemard, Rida Kheirallah, 2015, 2015 International Workshop on CMOS Variability (VARI).

Defining the Maximum Speed of CMOS Gate Library

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2002 .

Tool Box for Performance Driven Macrocell layout Synthesis

Daniel Auvergne, Nadine Azemard, Fernando Moraes, 1993 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Lars Svensson, Nadine Azemard, 2008 .

An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor Sizing

Daniel Auvergne, Nadine Azemard, Michel Robert, 1991 .

Path Selection for Delay and Power Performance Optimization

Daniel Auvergne, Nadine Azemard, Séverine Cremoux, 1998 .

SSTA with delay correlations

Philippe Maurine, Gilles Ducharme, Nadine Azemard, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

Computing delay correlations in SSTA

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Switching Current Modeling in CMOS Inverter for Speed and Power Estimation

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .