G. R. Mishra

发表

Application of CSMT gate for efficient reversible realization of binary to gray code converter circuit

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015, 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON).

Study of ECG Waveform and Development of an Algorithm for Removal of Power Line Interference

G. R. Mishra, Raghuvendra Pratap Tripathi, Ankita Tiwari, 2018, 2018 International Conference on Computational and Characterization Techniques in Engineering & Sciences (CCTES).

Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

G. R. Mishra, O. P. Singh, Sunil Kumar Ojha, 2018 .

Design and fabrication of a nano patch electrode for ECG using CNT/PDMS

Ankita Tiwari, G. R. Mishra, Raghuvendra Pratap Tripathi, 2017, 2017 International Conference on Computing Methodologies and Communication (ICCMC).

Design and implementation of a real time stress monitoring system with the help of ECG using Matlab tool

G. R. Mishra, Raghuvendra Pratap Tripathi, R. P. Tripathi, 2017, 2017 International Conference on Computer, Communications and Electronics (Comptelix).

A Novel Approach for Reversible Realization of 4 × 4 Bit Vedic Multiplier Circuit

Vandana Shukla, G. R. Mishra, R. K. Tiwari, 2020 .

Design of array multiplier circuit using reversible logic approach with optimized performance parameters

Vandana Shukla, G. R. Mishra, R. K. Tiwari, 2020 .

DAPSO and PSO-VAF in Linear Phase Digital Low Pass FIR Filter Design

G. R. Mishra, Mudit Shukla, 2014 .

A novel approach to design a redundant binary signed digit adder cell using reversible logic gates

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015, 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON).

Study of various data compression techniques used in lossless compression of ECG signals

G. R. Mishra, Raghuvendra Pratap Tripathi, 2017, 2017 International Conference on Computing, Communication and Automation (ICCCA).

Analysis and design of single ended SRAM cell for low-power operation

O. P. Singh, G. R. Mishra, Sunil Kumar Ojha, 2016, 2016 11th International Conference on Industrial and Information Systems (ICIIS).

Reversible Realization of N-bit Arithmetic Circuit for Low Power Loss ALU Applications

Vandana Shukla, O. P. Singh, G. R. Mishra, 2018 .

An Efficient Use of Memory Grouping Algorithm for Implementation of BIST in Self Test

P. R. Vaya, G. R. Mishra, Sunil Kumar Ojha, 2019 .

Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach

Vandana Shukla, O. P. Singh, G. R. Mishra, 2016, 2016 11th International Conference on Industrial and Information Systems (ICIIS).

Effect of Threshold Roll-Off on Static Noise Margin of Sram Cell

G. R. Mishra, O. P. Singh, Sunil Kumar Ojha, 2018 .

Realisation of optimised eight-bit binary shifter using reversible logic approach

Vandana Shukla, O. P. Singh, G. R. Mishra, 2017, Int. J. Serv. Technol. Manag..

A novel approach for reversible realization of 8-bit adder-subtractor circuit with optimized quantum cost

Vandana Shukla, O. P. Singh, G. R. Mishra, 2016, 2016 International Conference on Emerging Trends in Engineering, Technology and Science (ICETETS).

A New Reversible 'SMT' Gate and itsApplication to Design Low Power Circuits

G. R. Mishra, Monika Tiwari, O.P.Singh, 2015 .

An efficient approach for reversible realization of 1:4 demultiplexer circuit

Vandana Shukla, O. P. Singh, G. R. Mishra, 2016, 2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES).

Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015 .

A novel approach to design decimal to BCD encoder with reversible logic

Vandana Shukla, O. P. Singh, G. R. Mishra, 2014, 2014 International Conference on Power, Control and Embedded Systems (ICPCES).

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015, Int. J. Bus. Data Commun. Netw..

A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015 .

Design of DRAM having dummy cell sensing structure

P. R. Vaya, O. P. Singh, G. R. Mishra, 2015, 2015 National Conference on Recent Advances in Electronics & Computer Engineering (RAECE).

A Novel Approach for Reversible Realization of 3:8 Decoder Circuit with Optimized Performance Parameters

Vandana Shukla, O. P. Singh, G. R. Mishra, 2018, 2018 International Conference on Computational and Characterization Techniques in Engineering & Sciences (CCTES).