R. K. Tiwari

发表

Application of CSMT gate for efficient reversible realization of binary to gray code converter circuit

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015, 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON).

A Novel Approach for Reversible Realization of 4 × 4 Bit Vedic Multiplier Circuit

Vandana Shukla, G. R. Mishra, R. K. Tiwari, 2020 .

Design of array multiplier circuit using reversible logic approach with optimized performance parameters

Vandana Shukla, G. R. Mishra, R. K. Tiwari, 2020 .

A novel approach to design a redundant binary signed digit adder cell using reversible logic gates

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015, 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON).

Reversible Realization of N-bit Arithmetic Circuit for Low Power Loss ALU Applications

Vandana Shukla, O. P. Singh, G. R. Mishra, 2018 .

Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach

Vandana Shukla, O. P. Singh, G. R. Mishra, 2016, 2016 11th International Conference on Industrial and Information Systems (ICIIS).

A novel approach for reversible realization of 8-bit adder-subtractor circuit with optimized quantum cost

Vandana Shukla, O. P. Singh, G. R. Mishra, 2016, 2016 International Conference on Emerging Trends in Engineering, Technology and Science (ICETETS).

An efficient approach for reversible realization of 1:4 demultiplexer circuit

Vandana Shukla, O. P. Singh, G. R. Mishra, 2016, 2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES).

Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015 .

A novel approach to design decimal to BCD encoder with reversible logic

Vandana Shukla, O. P. Singh, G. R. Mishra, 2014, 2014 International Conference on Power, Control and Embedded Systems (ICPCES).

A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

Vandana Shukla, O. P. Singh, G. R. Mishra, 2015 .

Design and performance analysis for the reversible realization of adder/subtractor circuit

R. K. Tiwari, Vandana Shukla, O. Singh, 2017, 2017 International Conference on Emerging Trends in Computing and Communication Technologies (ICETCCT).

Novel Design of A 4 : 1 Multiplexer Circuit Using Reversible Logic

R. K. Tiwari, Vandana Shukla, O. Singh, 2013 .

A Novel Approach for 4-Bit Squaring Circuit Using Vedic Mathematics

R. K. Tiwari, Vandana Shukla, O. Singh, 2020 .