Davide Tasca

An all-digital architecture for low-jitter regulated delay lines

Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic

Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, 2010, EURASIP J. Embed. Syst..

A glitch-corrector circuit for low-spur ADPLLs

Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Noise Analysis and Minimization in Bang-Bang Digital PLLs

Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

An automatic retiming system for asynchronous fractional frequency dividers

Salvatore Levantino, Carlo Samori, Marco Zanuso, 2010, 6th Conference on Ph.D. Research in Microelectronics & Electronics.

Low-Power Divider Retiming in a

Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, 2011 .

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power

Giovanni Marzin, Salvatore Levantino, Carlo Samori, 2011, 2011 IEEE International Solid-State Circuits Conference.

Low-Power Divider Retiming in a 3–4 GHz Fractional-N PLL

Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power

Giovanni Marzin, Salvatore Levantino, Carlo Samori, 2011, IEEE Journal of Solid-State Circuits.