H. Kunishima

Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS devices

S. Ohnishi, N. Kawahara, Y. Kakuhara, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

High controllability and low cost APM process by one-bath type wet-bench for multi gate oxide pre-cleaning

T. Suzuki, H. Kunishima, S. Chikaki, 2000, Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130).

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 /spl mu/m CMOS generation

T. Takewaki, H. Kunishima, T. Horiuchi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).