F.F. Jamin

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Issues in NiSi-gated FDSOI device integration

Ying Zhang, M. Steen, Meikei Ieong, 2003, IEEE International Electron Devices Meeting 2003.

On the integration of CMOS with hybrid crystal orientations

K. Bernstein, P. Oldiges, M. Ieong, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..