Siti Zarina Md Naziri

The design revolution of logarithmic number system architecture

Rizalafande Che Ismail, Siti Zarina Md Naziri, Ali Yeon Md Shakaff, 2014, 2014 2nd International Conference on Electrical, Electronics and System Engineering (ICEESE).

Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture

Mohd Nazrin Md Isa, Rizalafande Che Ismail, Siti Zarina Md Naziri, 2021 .

Crypto-Core Design using Camellia Cipher

Mohd Nazrin Md Isa, Rizalafande Che Ismail, Siti Zarina Md Naziri, 2021 .

The FPGA implementation of multiplicative inverse value of GF(28) generator using Extended Euclid Algorithm (EEA) method for Advanced Encryption Standard (AES) algorithm

Siti Zarina Md Naziri, Yeong Chee Mei, 2011, 2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE).