S. Halle

Overcoming the challenges of 22-nm node patterning through litho-design co-optimization

Martin Burkhardt, S. Burns, C. Tabery, 2009, Advanced Lithography.

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

U. Gruening, D. Casarotto, J. Alsmeier, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

M. Raymond, M. Burkhardt, S. Paparao, 2008, 2008 IEEE International Electron Devices Meeting.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

Yongan Xu, Yunpeng Yin, Chiew-seng Koay, 2012, 2012 IEEE International Interconnect Technology Conference.