M. Colburn

Overcoming the challenges of 22-nm node patterning through litho-design co-optimization

Martin Burkhardt, S. Burns, C. Tabery, 2009, Advanced Lithography.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

BEOL process integration for the 7 nm technology node

F. Mont, T. Spooner, X. Zhang, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

10nm FINFET technology for low power and high performance applications

D. Chanemougame, P. Oldiges, B. Haran, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

M. Raymond, M. Burkhardt, S. Paparao, 2008, 2008 IEEE International Electron Devices Meeting.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

Yongan Xu, Yunpeng Yin, Chiew-seng Koay, 2012, 2012 IEEE International Interconnect Technology Conference.

56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme

E. Soda, T. Spooner, J. C. Arnold, 2012, 2012 IEEE International Interconnect Technology Conference.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

T. Spooner, M. Tagami, M. Colburn, 2011, 2011 IEEE International Interconnect Technology Conference.