Tadahiro Sasaki

SESSION XII: SEMI-CUSTOM ARRAY DESIGN

T. Terada, Yasuo Ikawa, Atsushi Kameyama, 1984 .

An 8-b slice GaAs bus logic LSI for a high-speed parallel processing system

T. Terada, Katsue Kawakyu, Tadahiro Sasaki, 1991 .

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

T. Terada, Yasuo Ikawa, Katsue Kawakyu, 1987 .

Building-cell design methodology for high-speed GaAs standard-cell LSIs

T. Terada, Tadahiro Sasaki, Nobuyuki Toyoda, 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

A 2 Gb/s GaAs 128-bit shift register using standard cells with 0.5 mu m WN/sub x/ gate MESFETs

T. Terada, Katsue Kawakyu, Tadahiro Sasaki, 1988, 10th Annual IEEE (GaAs IC) Symposium, Gallium Arsenide Integrated Circuit. Technical Digest 1988..

Cell-shifting compaction of building-cell methodology for high-speed GaAs standard-cell LSIs

T. Terada, Katsue Kawakyu, Tadahiro Sasaki, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.