Spiridon F. Beldianu

ASIC Design of Shared Vector Accelerators for Multicore Processors

Sotirios G. Ziavras, Spiridon F. Beldianu, 2014, 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing.

FPGA and ASIC square root designs for high performance and power efficiency

Sotirios G. Ziavras, Spiridon F. Beldianu, Shashank Suresh, 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

Versatile design of shared vector coprocessors for multicores

Sotirios G. Ziavras, Spiridon F. Beldianu, Christopher Dahlberg, 2012, Microprocess. Microsystems.

Performance-Energy Optimizations for Shared Vector Accelerators in Multicores

Sotirios G. Ziavras, Spiridon F. Beldianu, 2015, IEEE Transactions on Computers.

Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches

Eiji Oki, Roberto Rojas-Cessa, Sotirios G. Ziavras, 2009, 2009 Proceedings of 18th International Conference on Computer Communications and Networks.

Efficient on-chip vector processing for multicore processors

Sotirios G. Ziavras, Spiridon F. Beldianu, 2013, 2013 International Symposium on System on Chip (SoC).

On-chip Vector Coprocessor Sharing for Multicores

Sotirios G. Ziavras, Spiridon F. Beldianu, 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

Multicore-based vector coprocessor sharing for performance and energy gains

Sotirios G. Ziavras, Spiridon F. Beldianu, 2013, TECS.

Scheduling for input-queued packet switches by a re-configurable parallel match evaluator

Eiji Oki, Roberto Rojas-Cessa, Sotirios G. Ziavras, 2010, IEEE Communications Letters.