Jeong-Mo Hwang

发表

ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation

Tae-Kyun Kim, Se-Aug Jang, Jun-Mo Yang, 2000 .

Characteristics of Al/sub 2/O/sub 3/ gate dielectric prepared by atomic layer deposition for giga scale CMOS DRAM devices

In-Seok Yeo, Jae-Sung Roh, Jeong-Mo Hwang, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits

Hi-Deok Lee, Jeong-Mo Hwang, Sang-Bok Lee, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology

Jeong-Mo Hwang, Myoung-Jun Jang, Dae-Gwan Kang, 1999 .

Scalability of conventional and sidewall-sealed LOCOS technology for 256-Mbit DRAM array and periphery isolation

Mark Rodder, Ih-Chin Chen, Jeong-Mo Hwang, 1996, Advanced Lithography.

A 15ns 4Mb NVSRAM in 0.13u SONOS Technology

Jeong-Mo Hwang, M. Fliesler, D. Still, 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

Effects of Low Temperature Interlayer Dielectric Films on the Gate Oxide Quality of Deep Submicron MOSFET's

Jeong-Mo Hwang, Oh-Kyong Kwon, Young-Jong Lee, 1997 .

Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging

Jeong-Mo Hwang, Dae-Mann Kim, Young-Jong Lee, 1998 .

Plasma enhanced chemical vapor deposition Si-rich silicon oxynitride films for advanced self-aligned contact oxide etching in sub-0.25 μm ultralarge scale integration technology and beyond

Jeong-Mo Hwang, Jin-Woong Kim, Jeong-Ho Kim, 2000 .

Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters

Oh-Kyong Kwon, Jeong-Mo Hwang, Dae-Mann Kim, 1999 .

Experimental evidence for nonlucky electron model effect in 0.15-/spl mu/m NMOSFETs

Jeong-Mo Hwang, Sang-Gi Lee, Hi-Deok Lee, 2002 .

Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's

Jeong-Mo Hwang, Hi-Deok Lee, H. Lee, 1998 .

Azide-assisted terminal crosslinking of ionomeric blocks: Effects on morphology and proton conductivity

Tae-Hyun Kim, Jeong-Mo Hwang, Roshni Lilly Thankamony, 2012 .

Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS

Jeong-Mo Hwang, Jeong-Mo Hwang, G. Pollack, 1992, 1992 International Technical Digest on Electron Devices Meeting.

New Gate Electrodes for Fully-Depleted Soi/cmos; Tin and Poly Si-Ge

Jeong-Mo Hwang, G. Pollack, 1992, 1992 IEEE International SOI Conference.