Vasile Paraschiv

Double patterning with dual hard mask for 28-nm node devices and below

Hubert Hody, Vasile Paraschiv, E. Vecchio, 2013 .

Double patterning with dual hard mask for 28nm node devices and below

Hubert Hody, Vasile Paraschiv, Gustaf Winroth, 2013, Advanced Lithography.

Invited) Vertical Nanowire FET Integration and Device Aspects

Nadine Collaert, Aaron Thean, Tsvetan Ivanov, 2016 .

Gate double patterning strategies for 10-nm node FinFET devices

David Hellin, Hubert Hody, Vasile Paraschiv, 2015 .

STT MRAM patterning challenges

Vasile Paraschiv, W. Boullart, Eiichi Nishimura, 2013, Advanced Lithography.

Gate double patterning strategies for 10nm node FinFET devices

David Hellin, Hubert Hody, Vasile Paraschiv, 2014, Advanced Lithography.